All digital phase detector and corrector

{
  "publication_number": "US3889186A",
  "country": "US",
  "kind": "A",
  "title": "All digital phase detector and corrector",
  "abstract": "An improved apparatus for detecting and correcting phase errors using all digital means. Transitions from a pseudo-random digital input pulse train cause a digital sample-and-hold device to store a value representing a magnitude and direction of phase error between the input pulse train and an output pulse train. This error value controls a digital pulse source whose output frequency is proportional to the error value. An up/down counter, which is incrementing at a controlled rate many times faster than the frequency of the input pulse train, is caused to increase or decrease its incrementing rate at a rate determined by the pulse source output, and in a direction determined by the direction of the phase error. A gating circuit transforms the counter contents into a value which, when sampled at the instant of transition of the input pulse train, provides a value indicative of phase error magnitude and direction to the inputs of the sample-and-hold device. The output of the highest order stage of the counter is a square wave whose phase error is continually being detected and corrected in conformity with the phase of the input pulse train.",
  "claims": [
    "1. An apparatus for detecting and correcting phase error comprising: a frequency source; a binary counter coupled to said frequency source and incrementing at a rate Controlled by said frequency source; a source of input pulses; means coupled to said pulse source for detecting a transition in said input pulses; means responsive to said transition-detecting means and coupled to said counter for detecting the error, at the instant of said transition, between the value in said counter and a predetermined value and for converting the value in said counter to a value representing magnitude and direction of phase error when compared with the phase of said input pulse; and means responsive to said error-detecting means and coupled to said counter for varying said counter incrementing rate at a rate proportional to said error, thereby correcting said error.",
    "2. The apparatus of claim 1, wherein said error-detecting means includes a sample-and-hold circuit.",
    "3. The apparatus of claim 2, where said counter-rate-varying means includes at least one binary rate multiplier coupled to said sample-and-hold circuit.",
    "4. The apparatus of claim 3, wherein said counter-rate-varying means includes a pulse source driving said rate multiplier.",
    "5. The apparatus of claim 4, wherein said counter-rate-varying means includes means for communicating said magnitude of phase error to said rate multiplier, whereby said rate multiplier outputs a pulse train whose frequency is proportional to said magnitude of phase error.",
    "6. The apparatus of claim 5, wherein said counter-rate-varying means includes means for gating said pulse train from said rate multiplier to said counter, whereby the stepping rate of said counter will increase or decrease to lessen said magnitude of phase error."
  ],
  "cpc": [
    "G01R 25/00",
    "H03L 7/0992",
    "H04L 7/0331"
  ],
  "ipc": [
    "G01R 25/00",
    "H03L 7/099",
    "H04L 7/033"
  ],
  "assignees": [
    "United States Department of the Army"
  ],
  "inventors": [
    "Robin J Larson"
  ],
  "filing_date": "1973-11-27",
  "publication_date": "1975-06-10",
  "grant_date": "1975-06-10",
  "priority_date": "1973-11-27",
  "application_number": "US-41932973-A",
  "family_id": "23661789",
  "cited_by_count": 18,
  "citations": [
    "US3271688A",
    "US3544907A",
    "US3781695A"
  ]
}