Quantizing and dequantizing circuit with reduced size

{
  "publication_number": "US5635938A",
  "country": "US",
  "kind": "A",
  "title": "Quantizing and dequantizing circuit with reduced size",
  "abstract": "A quantizing and dequantizing circuit has a first memory circuit with integer addresses, in which reciprocal data are stored, and a second memory circuit, in which a quantization table of integers is stored. The Integers stored in the second memory circuit are provided to the first memory circuit as address signals, causing output of the corresponding reciprocal data. Data to be quantized are multiplied by the reciprocal data output by the first memory circuit. Data to be dequantized are multiplied by the integers output from the second memory circuit.",
  "claims": [
    "1. A quantizing and dequantizing circuit for quantizing first data and dequantizing second data, comprising: a first memory circuit with integer addresses, for storing, at each address, reciprocal data for quantizing said first data, and providing an output of said reciprocal data responsive to the address input, said first memory circuit storing said reciprocal data in a compressed form with leading zero-valued bits removed; a second memory circuit for storing a quantization table of integers, and providing output of said integers as said address input to said first memory circuit; a multiplier coupled to multiply said second data by the integers output from said second memory circuit, multiply said first data by reciprocals of said integers obtained from the reciprocal data output by said first memory circuit, and provide output of resulting products; and a zero padder, coupled to add leading zero-valued bits to the output of said first memory circuit in a quantity responsive to the output of said second memory circuit, before said output of said first memory circuit is furnished to said multiplier.",
    "2. The circuit of claim 1, wherein said reciprocal data is represented by a reciprocal of said integer address.",
    "3. The circuit of claim 1, wherein said first memory circuit is a read-only memory circuit and said second memory circuit is a read-write memory circuit.",
    "4. A quantizing and dequantizing circuit for quantizing first data and dequantizing second data, comprising: a first memory circuit with integer addresses, for storing, at each address, reciprocal data for quantizing said first data, and providing an output of said reciprocal data responsive to the address input, said first memory circuit storing said reciprocal data in a compressed form with leading zero-valued bits removed and with a single leading one-valued bit removed; a second memory circuit for storing a quantization table of integers, and providing an output of said integers as said address input to said first memory circuit; a multiplier coupled to multiply said second data by the integers output from said second memory circuit, multiply said first data by reciprocals of said integers obtained from the reciprocal data output by said first memory circuit, and provide output of resulting products; and a zero padder, coupled to add a single leading one-valued bit to the output of said first memory circuit, then also add leading zero-valued bits in a quantity responsive to the output of said second memory circuit, before said output of said first memory circuit is furnished to said multiplier.",
    "5. The circuit of claim 4, wherein said reciprocal data is represented by a reciprocal of said integer address.",
    "6. The circuit of claim 4, wherein said first memory circuit is a read-only memory circuit and said second memory circuit is a read-write memory circuit.",
    "7. A quantizing and dequantizing circuit for quantizing first data and dequantizing second data, comprising: a first memory circuit with integer addresses, for storing, at each address, reciprocal data for quantizing said first data, and providing an output of said reciprocal data responsive to the address input, said first memory circuit storing reciprocal data in a compressed form with leading zeros removed; a second memory circuit for storing a quantization table of integers, and providing an output of said integers as said address input to said first memory circuit; a multiplier coupled to multiply said second data by the integers output from said second memory circuit, multiply said first data by reciprocals of said integers obtained from the reciprocal data output by said first memory circuit, and provide output of resulting products; a first selector controlled by a control signal having a first state indicating quantization and a second state indicating dequantization, coupled to furnish the output of said first memory circuit to said multiplier when said control signal is in said first state, and furnish the output of said second memory circuit to said multiplier when said control signal is in said second state; a shifter, coupled to right-shift the output of said multiplier by a number of bits responsive to the output of said second memory circuit, and to output the shifted data; and a second selector, controlled by said control signal, coupled to select the shifted data output by said shifter when said control signal is in said first state, and to shift the output of said multiplier when said control signal is in said second state.",
    "8. The circuit of claim 7, wherein said first memory circuit stores reciprocal data in a compressed form with leading zero-valued bits removed and with one leading one-valued bit removed, further comprising: a logic-one node, coupled to add one leading one-valued bit to the output of said first memory circuit, before said output of said first memory circuit is furnished to said multiplier.",
    "9. The circuit of claim 7, wherein said reciprocal data is represented by a reciprocal of said integer address.",
    "10. The circuit of claim 7, wherein said first memory circuit is a read-only memory circuit and said second memory circuit is a read-write memory circuit.",
    "11. A method of quantizing first data and dequantizing second data, comprising the steps of: storing, in a first memory circuit having integer addresses, reciprocal data for quantizing said first data; storing, in a second memory circuit, a quantization table of integers; providing the integers stored in said second memory circuit to said first memory circuit as address signals, thereby causing an output of corresponding reciprocal data; multiplying said first data by reciprocals of said integers obtained from said reciprocal data, thereby generating quantized data; multiplying said second data by the integers output by said second memory circuit, thereby generating dequantized data; generating a control signal having a first state indicating quantization and a second state indicating dequantization; and selecting the output of said first memory circuit or the output of said second memory circuit responsive to said control signal.",
    "12. The method of claim 11, wherein said reciprocal data is represented by a reciprocal of said integer address.",
    "13. The method of claim 11, wherein said first memory circuit is a read-only memory circuit and said second memory circuit is a read-write memory circuit.",
    "14. A method of quantizing first data and dequantizing second data, comprising the steps of: storing, in a first memory circuit having integer addresses, reciprocal data for quantizing said first data, said first memory circuit storing reciprocal data in a compressed form with leading zero-valued bits removed; storing, in a second memory circuit, a quantization table of integers; providing the integers stored in said second memory circuit to said first memory circuit as address signals, thereby causing an output of corresponding reciprocal data; multiplying said first data by reciprocals of said integers obtained from said reciprocal data, thereby generating quantized data; multiplying said second data by the integers output by said second memory circuit, thereby generating dequantized data; and adding leading zero-valued bits to the output of said first memory circuit in quantities responsive to the integers output by said second memory circuit.",
    "15. The method of claim 11, wherein said first memory circuit stores reciprocal data in a compressed form with leading zero-valued bits removed.",
    "16. A method of quantizing first data and dequantizing second data, comprising the steps of: storing, in a first memory circuit having integer addresses, reciprocal data for quantizing said first data, said first memory circuit storing reciprocal data in a compressed form with leading zero-valued bits removed; storing, in a second memory circuit, a quantization table of integers; providing the integers stored in said second memory circuit to said first memory circuit as address signals, thereby causing an output of corresponding reciprocal data; multiplying said first data by reciprocals of said integers obtained from said reciprocal data, thereby generating quantized data; and multiplying said second data by the integers output by said second memory circuit, thereby generating dequantized data; right-shifting said quantized data by amounts responsive to the integers output by said second memory circuit.",
    "17. A method of quantizing first data and dequantizing second data, comprising the steps of: storing, in a first memory circuit having integer addresses, reciprocal data for quantizing said first data, said first memory circuit storing reciprocal data in a compressed form with leading zero-valued bits removed and with a single leading one-valued bit removed; storing, in a second memory circuit, a quantization table of integers; providing the integers stored in said second memory circuit to said first memory circuit as address signals, thereby causing an output of corresponding reciprocal data; multiplying said first data by reciprocals of said integers obtained from said reciprocal data, thereby generating quantized data; multiplying said second data by the integers output by said second memory circuit, thereby generating dequantized data; and adding a single leading one-valued bit to the output of said first memory circuit.",
    "18. The method of claim 17, comprising the further step of adding leading zero-valued bits to the output of said first memory circuit in a quantity responsive to the integers output by said second memory circuit.",
    "19. The method of claim 17, comprising the further step of right-shifting said quantized data by a number of bits responsive to the integers output by said second memory circuit.",
    "20. A quantizing and dequantizing circuit for quantizing first data and dequantizing second data, comprising: a first memory circuit storing reciprocal data for quantizing said first data: a second memory circuit storing a quantization table of integers for dequantizing said second data; a multiplier for multiplying said first data by said reciprocal data and for multiplying said second data by said integers; and a shifter for shifting an output of said multiplier according to the quantization table of integers.",
    "21. The circuit of claim 20, wherein the reciprocal data in said first memory circuit are selected by an address corresponding to an integer in the quantization table of integers.",
    "22. The circuit of claim 20, wherein the reciprocal data are stored in said first memory circuit in a compressed form with leading zero-valued bits removed.",
    "23. The circuit of claim 20, wherein the reciprocal data are stored in said first memory circuit in a compressed form with leading zero-valued bits removed and with one leading one-valued bit removed, further comprising: a logic-one node for adding a leading one-valued bit to the reciprocal data.",
    "24. A quantizing and dequantizing circuit for quantizing first data and dequantizing second data, comprising: a first memory circuit storing reciprocal data for quantizing said first data: a second memory circuit storing a quantization table of integers for dequantizing said second data; a padder for padding the reciprocal data and outputting padded reciprocal data; and a multiplier for multiplying said first data by said padded reciprocal data and for multiplying said second data by said integers.",
    "25. The circuit of claim 24, wherein the reciprocal data in said first memory circuit are selected by an address corresponding to an integer in the quantization table of integers.",
    "26. The circuit of claim 24, wherein the reciprocal data are stored in said first memory circuit in a compressed form with leading zero-valued bits removed.",
    "27. The circuit of claim 24, wherein the reciprocal data are stored in said first memory circuit in a compressed form with leading zero-valued bits removed and with one leading one-valued bit removed."
  ],
  "description_excerpt": "This invention relates to a quantizing and dequantizing circuit for use in, for example, a device that compresses and decompresses digitized image data.\n\nEfficient recording and transmission of digitized image data demands that the data be compressed. In one standard compression method, an image is divided into, for example, eight-by-eight pixel blocks. First, each block of pixel values is converted by a discrete cosine transformation (DCT) to spatial frequency values (DCT coefficients). The transformed data are next quantized by dividing the data by a set of values representing quantization step sizes, using different step sizes for different frequencies. The quantized data are then encoded by Huffman-type variable-length encoding, in which shorter codewords are assigned to frequently-occurring data and longer codewords to infrequently-occurring data.\n\nIn decompression, this procedure is followed in reverse. Huffman decoding is used to recover the quantized data, which are next dequantized by multiplication by the same step-size values as were used in quantization. Then an inverse discrete cosine transformation (IDCT) is applied to reconstruct the pixel values.\n\nDevices that perform image compression and decompression accordingly have a circuit that performs quantization during compression and dequantization during decompression. A conventional quantizing and dequantizing circuit comprises a memory that stores a set of step-size values, a hardware divider for dividing data by these values to quantize the data, and a hardware multiplier for multiplying data by the same values to dequantize the data.",
  "cpc": [
    "H04B 14/04",
    "H03M 7/3002",
    "H04N 19/124",
    "H04N 19/126",
    "H04N 19/60"
  ],
  "ipc": [
    "G06T 9/00",
    "H03M 7/30",
    "H03M 7/40",
    "H04B 14/04",
    "H04N 1/41",
    "H04N 19/00",
    "H04N 19/42",
    "H04N 19/423",
    "H04N 19/625",
    "H04N 19/91"
  ],
  "assignees": [
    "Oki Electric Industry Co Ltd"
  ],
  "inventors": [
    "Eiji Komoto"
  ],
  "filing_date": "1994-12-28",
  "publication_date": "1997-06-03",
  "grant_date": "1997-06-03",
  "priority_date": "1993-12-28",
  "application_number": "US-36546794-A",
  "family_id": "18316062",
  "cited_by_count": 25,
  "citations": [
    "US4694417A",
    "US4920411A",
    "US4658239A",
    "US5136290A",
    "US5243342A",
    "JPH05110863A",
    "US5430556A"
  ]
}