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Patent · US2008252265A1 · A1 · US

Detection circuit

(11) Publication number
US2008252265A1
(21) Application number
12/031,403
(22) Filing date
2008-02-14
(30) Priority date
2007-02-16
(43) Publication date
2008-10-16
(51) IPC
G01R 19/00; H02J 7/04
(52) CPC
  • H02M Apparatus for conversion between AC and AC, between AC and DC, or between DC and DC, and for use with mains or similar power supply systems; conversion of DC or AC input power into surge output power; control or regulation thereof: 3/156, 1/0009
  • B66F Hoisting, lifting, hauling or pushing, not otherwise provided for, e.g. devices which apply a lifting or pushing force directly to the surface of a load: 9/08, 9/122, 9/195, 9/22
  • G01R Measuring electric variables; measuring magnetic variables: 19/16542
(73) Assignee
Fujitsu Ltd
(72) Inventors
Masatoshi Kokubun; Takashi Matsumoto; Hidenobu Ito
(54) Title
Detection circuit
(57) Abstract

A detection circuit that reduces circuit scale. A plurality of current amplifiers respectively generate a plurality of detection signals corresponding to current flowing to a plurality of resistors. An error amplifier coupled to the plurality of current amplifiers compares the plurality of detection signals with a plurality of reference signals, respectively, to generate an error signal based on the comparison.

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Claims (1)

  1. A detection circuit for detecting current flowing to a plurality of resistors, the detection circuit comprising: a plurality of current amplifiers, respectively coupled to the plurality of resistors, which generate a plurality of detection signals, wherein each of the plurality of current amplifiers generates a corresponding one of the plurality of detection signals in accordance with the current flowing to a corresponding one of the plurality of resistors; and an error amplifier, coupled to the plurality of current amplifiers, which compares the plurality of detection signals with a plurality of reference signals, each associated with the corresponding one of the plurality of detection signals, and generates an error signal based on the comparison. 2. The detection circuit according to claim 1, wherein the error amplifier includes: a first input terminal which receives a comparison reference signal; a plurality of second input terminals which receive the plurality of detection signals generated by the plurality of current amplifiers, the comparison reference signal being set based on the plurality of reference signals, and the plurality of detection signals having different offsets; a bias circuit, coupled to the first input terminal and the plurality of second input terminals, which generates bias current corresponding to the offsets of the plurality of detection signals; and an error amplifier circuit, coupled to the bias circuit, the first input terminal, and the plurality of second input terminals, which generates the error signal in accordance with the difference between the comparison reference signal and the one of the plurality of detection signals having a lower signal level, wherein the error amplifier circuit corrects the offsets of the plurality of detection signals with the bias current. 3. The detection circuit according to claim 2, wherein the error amplifier circuit further includes: a differential amplifier which includes first and second transistors; a plurality of third transistors coupled to the first transistor and respectively responsive to the plurality of detection signals; a fourth transistor coupled to the second transistor and responsive to the comparison reference signal; and a fifth transistor which transmits the bias current generated by the bias current to the plurality of third transistors. 4. A detection circuit for incorporation in an electronic device for detecting input current supplied to the electronic device and charging current supplied to a rechargeable battery coupled to the electronic device, the detection circuit comprising: a first current amplifier which detects the input current and generates a first detection signal; a second current amplifier which detects the charging current and generates a second detection signal; and an error amplifier which generates an error signal based on the first detection signal, the second detection signal, and a comparison reference signal, the comparison reference signal being set based on a first reference signal corresponding to the input current and a second reference signal corresponding to the charging current, wherein the error amplifier generates the error signal in accordance with the difference between the comparison reference signal and one of the first and second detection signals. 5. The detection circuit according to claim 4, wherein the error amplifier includes: a first input terminal which receives the comparison reference signal; a second input terminal which receives the first detection signal generated by the first current amplifier; a third input terminal which receives the second detection signal generated by the second current amplifier, with the first and second detection signals having different offsets; a bias circuit, coupled to the first to third input terminals, which generates bias current corresponding to the offsets of the first and second detection signals; and an error amplifier circuit, coupled to the bias circuit and the first to third input terminals, which generates the error signal in accordance with the difference between the comparison reference signal and the one of the first and second detection signals having a lower signal level, wherein the error amplifier circuit corrects the offsets of the first and second detection signals with the bias current. 6. The detection circuit according to claim 5, wherein the error amplifier circuit includes: a differential amplifier which includes first and second transistors; a third transistor coupled to the first transistor and responsive to the first detection signal; a fourth transistor coupled to the first transistor and responsive to the second detection signal; a fifth transistor coupled to the second transistor and responsive to the comparison reference signal; and a sixth transistor which transmits the bias current generated by the bias current to the third and the fourth transistors. 7. A detection circuit for detecting a first current flowing to a first resistor and a second current flowing to a second resistor, which is coupled to the first resistor, the detection circuit comprising: a first current amplifier, coupled to the first resistor, which generates a first detection signal corresponding to the first current flowing to the first resistor; a second current amplifier, coupled to the second resistor, which generates a second detection signal corresponding to the second current flowing to the second resistor; a subtractor which receives a first reference signal, which corresponds to the first current, and a second reference signal, which corresponds to the second current, and generates first and second computation signals indicating a relative level difference of the first and second reference signals; a computing unit, coupled to the subtractor and operably coupled to the first current amplifier, which generates a third computation signal with the first detection signal and the first and second computation signals; and an error amplifier, coupled to the computing unit and the second current amplifier, which generates an error signal in accordance with the difference between one of the first and second reference signals and one of the third computation signal and second detection signal. 8. The detection circuit according to claim 7, further comprising: a first level shift circuit, coupled to the first current amplifier and the computing unit, which converts the first detection signal to a first conversion signal and provides the first conversion signal to the computing unit; a second level shift circuit, coupled to the computing unit, which converts the first reference signal to a second conversion signal and provides the second conversion signal to the computing unit; and a third level shift circuit, coupled to the computing unit, which converts the second reference signal to a third conversion signal and provides the third conversion signal to the computing unit; wherein the first, second, and third conversion signals each have a level corresponding to a fluctuation range of the second detection signal generated by the second current amplifier. 9. The detection circuit according to claim 7, wherein the error amplifier includes: a first input terminal which receives a comparison reference signal; a second input terminal which receives the third computation signal generated by the computing unit; a third input terminal which receives the second detection signal generated by the second current amplifier, the comparison reference signal being set to the first reference signal or the second reference signal, and the third computation signal and the second detection signal having different offsets; a bias circuit, coupled to the first to third input terminals, which generates a bias current corresponding to the offset of the third computation signal and the offset of the second detection signal; and an error amplifier circuit, coupled to the bias circuit and the first to third input terminals, which generates the error signal in accordance with the difference between the comparison reference signal and the one of the third computation signal and the second detection signal having a lower signal level, the error amplifier circuit correcting the offset of the third computation signal and the offset of the second detection signal with the bias current. 10. The detection circuit according to claim 9, wherein the error amplifier circuit includes: a differential amplifier which includes first and second transistors; a third transistor coupled to the first transistor and responsive to the third computation signal; a fourth transistor coupled to the first transistor and responsive to the second detection signal; a fifth transistor coupled to the second transistor and responsive to the comparison reference signal; and a sixth transistor which transmits the bias current generated by the bias current to the third and fourth transistors. 11. A power supply system comprising: an external power supply which generates a first output voltage for a direct current and varies the first output voltage in accordance with a control current; and an electronic device connectable to the external power supply and a rechargeable battery which generates a second output voltage, wherein the rechargeable battery is chargeable by a charging current supplied from the external power supply, the electronic device including: a system circuit operated by at least one of the first output voltage generated by the external power supply and the second output voltage generated by the rechargeable battery; and a detection circuit which detects the first output voltage, a first output current corresponding to the first output voltage, the second output voltage, and the charging current, the detection circuit including: an error amplifier which generates an error signal in accordance with the difference between a comparison reference signal and at least two of the first output voltage, the first output current, the second output voltage, and the charging current; and a current control circuit which generates the control current based on the error signal. 12. The power supply system according to claim 11, wherein: the detection circuit further includes a first current amplifier which generates a first detection signal corresponding to the first output current, and a second current amplifier which generates a second detection signal corresponding to the charging current; and the error amplifier includes: a first input terminal which receives the comparison reference signal; a second input terminal which receives the first detection signal; a third input terminal which receives the second detection signal, the first and second detection signals having different offsets; a bias circuit, coupled to the first to third input terminals, which generates a bias current corresponding to the offsets of the first and second detection signals; and an error amplifier circuit, coupled to the bias circuit and the first to third input terminals, which generates the error signal in accordance with the difference between the comparison reference signal and the one of the first and second detection signals having a lower signal level, the error amplifier circuit correcting the offsets of the first and second detection signals with the bias current. 13. A power supply system comprising: an external power supply which generates a first output voltage for a direct current and varies the first output voltage in accordance with a control current; and an electronic device connectable to the external power supply and a rechargeable battery which generates a second output voltage, wherein the rechargeable battery is chargeable by a charging current supplied from the external power supply, the electronic device including: a system circuit operated by at least one of the first output voltage generated by the external power supply and the second output voltage generated by the rechargeable battery; a detection circuit which generates the control current; a first resistor which enables the flow of a first output current corresponding to the first output voltage; and a second resistor, coupled between the first resistor and the rechargeable battery, which enables the flow of the charging current supplied to the secondary current, wherein the detection circuit includes: a first current amplifier which generates a first detection signal corresponding to the first output current flowing to the first resistor; a second current amplifier which generates a second detection signal corresponding to the charging current flowing to the second resistor; a subtracter which receives a first reference signal, which corresponds to the first output current, and a second reference signal, which corresponds to the charging current, and generates first and second computation signals indicating a relative level difference of the first and second reference signals; a computing unit, coupled to the subtracter and operably coupled to the first current amplifier, which generates a third computation signal with the first detection signal and the first and second computation signals; an error amplifier, coupled to the computing unit and the second current amplifier, which generates an error signal in accordance with the difference between one of the first and second reference signals and one of the third computation signal and second detection signal; and a current control circuit which generates the control current based on the error signal. 14. The power supply system, according to claim 13, wherein the detection circuit further includes: a first level shift circuit, coupled to the first current amplifier and the computing unit, which converts the first detection signal to a first conversion signal and provides the first conversion signal to the computing unit; a second level shift circuit, coupled to the computing unit, which converts the first reference signal to a second conversion signal and provides the second conversion signal to the computing unit; and a third level shift circuit, coupled to the computing unit, which converts the second reference signal to a third conversion signal and provides the third conversion signal to the computing unit, wherein the first, second, and third conversion signals each have a level corresponding to a fluctuation range of the second detection signal generated by the second current amplifier. 15. The power supply system according to claim 13, wherein the error amplifier includes: a first input terminal which receives a comparison reference signal; a second input terminal which receives the third computation signal generated by the computing unit; a third input terminal which receives the second detection signal generated by the second current amplifier, the comparison reference signal being set to the first reference signal or the second reference signal, and the third computation signal and the second detection signal having different offsets; a bias circuit, coupled to the first to third input terminals, which generates a bias current corresponding to the offset of the third computation signal and the offset of the second detection signal; and an error amplifier circuit, coupled to the bias circuit and the first to third input terminals, which generates the error signal in accordance with the difference between the comparison reference signal the one of the third computation signal and the second detection signal having a lower signal level, the error amplifier circuit correcting the offset of the third computation signal and the offset of the second detection signal with the bias current.

Description

This application invention relates to a detection circuit, and more specifically, to a detection circuit incorporated in a power supply system.

A portable electronic device such as a notebook computer is normally operated by a battery, which is installed in the electronic device, or an external power supply, such as an AC adapter. The battery, or rechargeable battery, is charged by a charging circuit incorporated in the electronic device. Japanese Patent No. 3428955 discloses a charging circuit for charging a rechargeable battery with charging current supplied from an external power supply. The operation of the conventional charging circuit will now be described with reference to FIG. 1.

A charging circuit 11 is incorporated in an electronic device. DC adapter voltage VAC is supplied to the charging circuit 11 from an input power adapter 12 coupled to the electronic device. The charging circuit 11 is a DC/DC converter that generates output voltage V out from the adapter voltage VAC. The charging circuit 11 controls the output voltage V out based on a detection value of an output current I out or the like. More specifically, the charging circuit 11 includes current amplifiers 13 a and 13 b. The current amplifier 13 a is coupled to the two ends of a resistor R 1 to detect the output current I out. The current amplifier 13 b is coupled to the two ends of a resistor R 2 to detecting charging current I chg, which is supplied to a battery BT. The current amplifiers 13 a and 13 b are respectively coupled to error amplifiers 14 a and 14 b.

Citations (3)

  • US5808444A
  • US6246215B1
  • US7626371B2
Record as JSON
{
  "publication_number": "US2008252265A1",
  "country": "US",
  "kind": "A1",
  "title": "Detection circuit",
  "abstract": "A detection circuit that reduces circuit scale. A plurality of current amplifiers respectively generate a plurality of detection signals corresponding to current flowing to a plurality of resistors. An error amplifier coupled to the plurality of current amplifiers compares the plurality of detection signals with a plurality of reference signals, respectively, to generate an error signal based on the comparison.",
  "claims": [
    "1. A detection circuit for detecting current flowing to a plurality of resistors, the detection circuit comprising: a plurality of current amplifiers, respectively coupled to the plurality of resistors, which generate a plurality of detection signals, wherein each of the plurality of current amplifiers generates a corresponding one of the plurality of detection signals in accordance with the current flowing to a corresponding one of the plurality of resistors; and an error amplifier, coupled to the plurality of current amplifiers, which compares the plurality of detection signals with a plurality of reference signals, each associated with the corresponding one of the plurality of detection signals, and generates an error signal based on the comparison. 2. The detection circuit according to claim 1, wherein the error amplifier includes: a first input terminal which receives a comparison reference signal; a plurality of second input terminals which receive the plurality of detection signals generated by the plurality of current amplifiers, the comparison reference signal being set based on the plurality of reference signals, and the plurality of detection signals having different offsets; a bias circuit, coupled to the first input terminal and the plurality of second input terminals, which generates bias current corresponding to the offsets of the plurality of detection signals; and an error amplifier circuit, coupled to the bias circuit, the first input terminal, and the plurality of second input terminals, which generates the error signal in accordance with the difference between the comparison reference signal and the one of the plurality of detection signals having a lower signal level, wherein the error amplifier circuit corrects the offsets of the plurality of detection signals with the bias current. 3. The detection circuit according to claim 2, wherein the error amplifier circuit further includes: a differential amplifier which includes first and second transistors; a plurality of third transistors coupled to the first transistor and respectively responsive to the plurality of detection signals; a fourth transistor coupled to the second transistor and responsive to the comparison reference signal; and a fifth transistor which transmits the bias current generated by the bias current to the plurality of third transistors. 4. A detection circuit for incorporation in an electronic device for detecting input current supplied to the electronic device and charging current supplied to a rechargeable battery coupled to the electronic device, the detection circuit comprising: a first current amplifier which detects the input current and generates a first detection signal; a second current amplifier which detects the charging current and generates a second detection signal; and an error amplifier which generates an error signal based on the first detection signal, the second detection signal, and a comparison reference signal, the comparison reference signal being set based on a first reference signal corresponding to the input current and a second reference signal corresponding to the charging current, wherein the error amplifier generates the error signal in accordance with the difference between the comparison reference signal and one of the first and second detection signals. 5. The detection circuit according to claim 4, wherein the error amplifier includes: a first input terminal which receives the comparison reference signal; a second input terminal which receives the first detection signal generated by the first current amplifier; a third input terminal which receives the second detection signal generated by the second current amplifier, with the first and second detection signals having different offsets; a bias circuit, coupled to the first to third input terminals, which generates bias current corresponding to the offsets of the first and second detection signals; and an error amplifier circuit, coupled to the bias circuit and the first to third input terminals, which generates the error signal in accordance with the difference between the comparison reference signal and the one of the first and second detection signals having a lower signal level, wherein the error amplifier circuit corrects the offsets of the first and second detection signals with the bias current. 6. The detection circuit according to claim 5, wherein the error amplifier circuit includes: a differential amplifier which includes first and second transistors; a third transistor coupled to the first transistor and responsive to the first detection signal; a fourth transistor coupled to the first transistor and responsive to the second detection signal; a fifth transistor coupled to the second transistor and responsive to the comparison reference signal; and a sixth transistor which transmits the bias current generated by the bias current to the third and the fourth transistors. 7. A detection circuit for detecting a first current flowing to a first resistor and a second current flowing to a second resistor, which is coupled to the first resistor, the detection circuit comprising: a first current amplifier, coupled to the first resistor, which generates a first detection signal corresponding to the first current flowing to the first resistor; a second current amplifier, coupled to the second resistor, which generates a second detection signal corresponding to the second current flowing to the second resistor; a subtractor which receives a first reference signal, which corresponds to the first current, and a second reference signal, which corresponds to the second current, and generates first and second computation signals indicating a relative level difference of the first and second reference signals; a computing unit, coupled to the subtractor and operably coupled to the first current amplifier, which generates a third computation signal with the first detection signal and the first and second computation signals; and an error amplifier, coupled to the computing unit and the second current amplifier, which generates an error signal in accordance with the difference between one of the first and second reference signals and one of the third computation signal and second detection signal. 8. The detection circuit according to claim 7, further comprising: a first level shift circuit, coupled to the first current amplifier and the computing unit, which converts the first detection signal to a first conversion signal and provides the first conversion signal to the computing unit; a second level shift circuit, coupled to the computing unit, which converts the first reference signal to a second conversion signal and provides the second conversion signal to the computing unit; and a third level shift circuit, coupled to the computing unit, which converts the second reference signal to a third conversion signal and provides the third conversion signal to the computing unit; wherein the first, second, and third conversion signals each have a level corresponding to a fluctuation range of the second detection signal generated by the second current amplifier. 9. The detection circuit according to claim 7, wherein the error amplifier includes: a first input terminal which receives a comparison reference signal; a second input terminal which receives the third computation signal generated by the computing unit; a third input terminal which receives the second detection signal generated by the second current amplifier, the comparison reference signal being set to the first reference signal or the second reference signal, and the third computation signal and the second detection signal having different offsets; a bias circuit, coupled to the first to third input terminals, which generates a bias current corresponding to the offset of the third computation signal and the offset of the second detection signal; and an error amplifier circuit, coupled to the bias circuit and the first to third input terminals, which generates the error signal in accordance with the difference between the comparison reference signal and the one of the third computation signal and the second detection signal having a lower signal level, the error amplifier circuit correcting the offset of the third computation signal and the offset of the second detection signal with the bias current. 10. The detection circuit according to claim 9, wherein the error amplifier circuit includes: a differential amplifier which includes first and second transistors; a third transistor coupled to the first transistor and responsive to the third computation signal; a fourth transistor coupled to the first transistor and responsive to the second detection signal; a fifth transistor coupled to the second transistor and responsive to the comparison reference signal; and a sixth transistor which transmits the bias current generated by the bias current to the third and fourth transistors. 11. A power supply system comprising: an external power supply which generates a first output voltage for a direct current and varies the first output voltage in accordance with a control current; and an electronic device connectable to the external power supply and a rechargeable battery which generates a second output voltage, wherein the rechargeable battery is chargeable by a charging current supplied from the external power supply, the electronic device including: a system circuit operated by at least one of the first output voltage generated by the external power supply and the second output voltage generated by the rechargeable battery; and a detection circuit which detects the first output voltage, a first output current corresponding to the first output voltage, the second output voltage, and the charging current, the detection circuit including: an error amplifier which generates an error signal in accordance with the difference between a comparison reference signal and at least two of the first output voltage, the first output current, the second output voltage, and the charging current; and a current control circuit which generates the control current based on the error signal. 12. The power supply system according to claim 11, wherein: the detection circuit further includes a first current amplifier which generates a first detection signal corresponding to the first output current, and a second current amplifier which generates a second detection signal corresponding to the charging current; and the error amplifier includes: a first input terminal which receives the comparison reference signal; a second input terminal which receives the first detection signal; a third input terminal which receives the second detection signal, the first and second detection signals having different offsets; a bias circuit, coupled to the first to third input terminals, which generates a bias current corresponding to the offsets of the first and second detection signals; and an error amplifier circuit, coupled to the bias circuit and the first to third input terminals, which generates the error signal in accordance with the difference between the comparison reference signal and the one of the first and second detection signals having a lower signal level, the error amplifier circuit correcting the offsets of the first and second detection signals with the bias current. 13. A power supply system comprising: an external power supply which generates a first output voltage for a direct current and varies the first output voltage in accordance with a control current; and an electronic device connectable to the external power supply and a rechargeable battery which generates a second output voltage, wherein the rechargeable battery is chargeable by a charging current supplied from the external power supply, the electronic device including: a system circuit operated by at least one of the first output voltage generated by the external power supply and the second output voltage generated by the rechargeable battery; a detection circuit which generates the control current; a first resistor which enables the flow of a first output current corresponding to the first output voltage; and a second resistor, coupled between the first resistor and the rechargeable battery, which enables the flow of the charging current supplied to the secondary current, wherein the detection circuit includes: a first current amplifier which generates a first detection signal corresponding to the first output current flowing to the first resistor; a second current amplifier which generates a second detection signal corresponding to the charging current flowing to the second resistor; a subtracter which receives a first reference signal, which corresponds to the first output current, and a second reference signal, which corresponds to the charging current, and generates first and second computation signals indicating a relative level difference of the first and second reference signals; a computing unit, coupled to the subtracter and operably coupled to the first current amplifier, which generates a third computation signal with the first detection signal and the first and second computation signals; an error amplifier, coupled to the computing unit and the second current amplifier, which generates an error signal in accordance with the difference between one of the first and second reference signals and one of the third computation signal and second detection signal; and a current control circuit which generates the control current based on the error signal. 14. The power supply system, according to claim 13, wherein the detection circuit further includes: a first level shift circuit, coupled to the first current amplifier and the computing unit, which converts the first detection signal to a first conversion signal and provides the first conversion signal to the computing unit; a second level shift circuit, coupled to the computing unit, which converts the first reference signal to a second conversion signal and provides the second conversion signal to the computing unit; and a third level shift circuit, coupled to the computing unit, which converts the second reference signal to a third conversion signal and provides the third conversion signal to the computing unit, wherein the first, second, and third conversion signals each have a level corresponding to a fluctuation range of the second detection signal generated by the second current amplifier. 15. The power supply system according to claim 13, wherein the error amplifier includes: a first input terminal which receives a comparison reference signal; a second input terminal which receives the third computation signal generated by the computing unit; a third input terminal which receives the second detection signal generated by the second current amplifier, the comparison reference signal being set to the first reference signal or the second reference signal, and the third computation signal and the second detection signal having different offsets; a bias circuit, coupled to the first to third input terminals, which generates a bias current corresponding to the offset of the third computation signal and the offset of the second detection signal; and an error amplifier circuit, coupled to the bias circuit and the first to third input terminals, which generates the error signal in accordance with the difference between the comparison reference signal the one of the third computation signal and the second detection signal having a lower signal level, the error amplifier circuit correcting the offset of the third computation signal and the offset of the second detection signal with the bias current."
  ],
  "description_excerpt": "This application invention relates to a detection circuit, and more specifically, to a detection circuit incorporated in a power supply system.\n\nA portable electronic device such as a notebook computer is normally operated by a battery, which is installed in the electronic device, or an external power supply, such as an AC adapter. The battery, or rechargeable battery, is charged by a charging circuit incorporated in the electronic device. Japanese Patent No. 3428955 discloses a charging circuit for charging a rechargeable battery with charging current supplied from an external power supply. The operation of the conventional charging circuit will now be described with reference to FIG. 1.\n\nA charging circuit 11 is incorporated in an electronic device. DC adapter voltage VAC is supplied to the charging circuit 11 from an input power adapter 12 coupled to the electronic device. The charging circuit 11 is a DC/DC converter that generates output voltage V out from the adapter voltage VAC. The charging circuit 11 controls the output voltage V out based on a detection value of an output current I out or the like. More specifically, the charging circuit 11 includes current amplifiers 13 a and 13 b. The current amplifier 13 a is coupled to the two ends of a resistor R 1 to detect the output current I out. The current amplifier 13 b is coupled to the two ends of a resistor R 2 to detecting charging current I chg, which is supplied to a battery BT. The current amplifiers 13 a and 13 b are respectively coupled to error amplifiers 14 a and 14 b.",
  "cpc": [
    "H02M 3/156",
    "B66F 9/08",
    "B66F 9/122",
    "B66F 9/195",
    "B66F 9/22",
    "G01R 19/16542",
    "H02M 1/0009"
  ],
  "ipc": [
    "G01R 19/00",
    "H02J 7/04"
  ],
  "assignees": [
    "Fujitsu Ltd"
  ],
  "inventors": [
    "Masatoshi Kokubun",
    "Takashi Matsumoto",
    "Hidenobu Ito"
  ],
  "filing_date": "2008-02-14",
  "publication_date": "2008-10-16",
  "priority_date": "2007-02-16",
  "application_number": "US-3140308-A",
  "family_id": "39783134",
  "cited_by_count": 15,
  "citations": [
    "US5808444A",
    "US6246215B1",
    "US7626371B2"
  ]
}

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