Boosting circuit of charge pump type and boosting method

{
  "publication_number": "US2011254616A1",
  "country": "US",
  "kind": "A1",
  "title": "Boosting circuit of charge pump type and boosting method",
  "abstract": "A boosting circuit of charge pump type includes: charging portion for applying an input voltage to a first capacitor; double boosting portion for applying the input voltage to a second capacitor and applying a sum of the input voltage and a voltage across the first capacitor to an output capacitor in a first predetermined period after start of a boosting operation; and triple boosting portion for repeating in order, after end of the first predetermined period, a step of applying the sum of the input voltage and the voltage across the first capacitor to the second capacitor and a step of applying a sum of the voltage across the first capacitor and a voltage across the second capacitor to the output capacitor.",
  "claims": [
    "1. A boosting circuit of charge pump type for boosting an input voltage to a voltage three or higher integer times, the circuit comprising: a charging portion which applies the input voltage to a first capacitor; a double boosting portion which, in a first predetermined period after start of a boosting operation, applies the input voltage to a second capacitor and applies a sum of the input voltage and a voltage across the first capacitor to an output capacitor; and a triple boosting portion which repeats in order, after end of the first predetermined period, a step of applying the sum of the input voltage and the voltage across the first capacitor to the second capacitor and a step of applying a sum of the voltage across the first capacitor and a voltage across the second capacitor to the output capacitor. 2. The boosting circuit according to claim 1, wherein: in the first predetermined period, a first step for double boosting in which the charging portion applies the input voltage to the first capacitor and a second step for double boosting in which the double boosting portion applies the sum of the input voltage and the voltage across the first capacitor to the output capacitor are repeated in that order, and the double boosting portion applies the input voltage to the second capacitor both in the first and second steps for double boosting; and after the end of the first predetermined period, a first step for triple boosting in which the charging portion applies the input voltage to the first capacitor, a second step for triple boosting in which the triple boosting portion applies the sum of the input voltage and the voltage across the first capacitor to the second capacitor, a third step for triple boosting in which the charging portion apply the input voltage to the first capacitor, and a fourth step for triple boosting in which the triple boosting portion applies the sum of the voltage across the first capacitor and the voltage across the second capacitor to the output capacitor are repeated in that order. 3. The boosting circuit according to claim 2, comprising: a first switch element A that is connected at one end to a non-reference potential side input terminal of the input voltage and at the other end to either one of terminals of the first capacitor, is turned on in the first step for double boosting, the first step for triple boosting, and the third step for triple boosting, and is turned off in the second step for double boosting, the second step for triple boosting, and the fourth step for triple boosting; a first switch element B that is connected at one end to a reference potential side input terminal of the input voltage and at the other end to the other terminal of the first capacitor, is turned on in the first step for double boosting, the first step for triple boosting, and the third step for triple boosting, and is turned off in the second step for double boosting, the second step for triple boosting, and the fourth step for triple boosting; a second switch element A that is connected at one end to the either one of terminals of the second capacitor and at the other end to the one terminal of the first capacitor, is turned on in the second step for triple boosting, and is turned off in the first predetermined period, the first step for triple boosting, the third step for triple boosting, and the fourth step for triple boosting; a second switch element B that is connected at one end to the non-reference potential side input terminal of the input voltage and at the other end to the other terminal of the first capacitor, is turned on in the second step for triple boosting, and is turned off in the first predetermined period, the first step for triple boosting, the third step for triple boosting, and the fourth step for triple boosting; a third switch element A that is connected at one end to either one of terminals of the output capacitor and at the other end to the one terminal of the first capacitor, is turned on in the second step for double boosting and the fourth step for triple boosting, and is turned off in the first step for double boosting, the first step for triple boosting, the second step for triple boosting, and the third step for triple boosting; a third switch element B that is connected at one end to the one terminal of the second capacitor and at the other end to the other terminal of the first capacitor, is turned on in the second step for double boosting and the fourth step for triple boosting, and is turned off in the first step for double boosting, the first step for triple boosting, the second step for triple boosting, and the third step for triple boosting; and a fourth switch element that is connected at one end to the non-reference potential side input terminal of the input voltage and at the other end to the one terminal of the second capacitor, is turned on in the first predetermined period, and is turned off after the end of the first predetermined period, and wherein the charging portion is composed of the first switch element A and the first switch element B, the double boosting portion is composed of the third switch element A, the third switch element B, and the fourth switch element, and the triple boosting portion is composed of the second switch element A, the second switch element B, the third switch element A, and the third switch element B. 4. The boosting circuit according to claim 3, wherein the first switch element A, the first switch element B, the second switch element A, the second switch element B, the third switch element A, the third switch element B, and the fourth switch element are turned on/off in synchronism with a clock. 5. The boosting circuit according to claim 3, wherein: the first switch element A, the first switch element B, the second switch element A, the second switch element B, the third switch element A, the third switch element B, and the fourth switch element are formed in a semiconductor integrated circuit; and the first capacitor, the second capacitor, and the output capacitor are externally connected to the semiconductor integrated circuit. 6. The boosting circuit according to claim 3, wherein an input capacitor is arranged between the non-reference potential side input terminal and the reference potential side input terminal, the input voltage being always applied to the input capacitor. 7. The boosting circuit according to claim 1, wherein in a second predetermined period that follows the end of the first predetermined period, the triple boosting portion repeats in order a step of applying the sum of the input voltage and the voltage across the first capacitor to the second capacitor and a step of applying the sum of the voltage across the first capacitor and the voltage across the second capacitor to a third capacitor, the boosting circuit further comprising quadruple boosting portion for repeating in order, after end of the second predetermined period, a step of applying the sum of the input voltage and the voltage across the first capacitor to the second capacitor, a step of applying the sum of the voltage across the first capacitor and the voltage across the second capacitor to the third capacitor, and a step of applying a sum of the voltage across the first capacitor and a voltage across the third capacitor to the output capacitor. 8. The boosting circuit according to claim 7, wherein: in the first predetermined period, a first step for double boosting in which the charging portion applies the input voltage to the first capacitor and a second step for double boosting in which the double boosting portion applies the sum of the input voltage and the voltage across the first capacitor to the output capacitor are repeated in that order, and the double boosting portion applies the input voltage to the second capacitor both in the first and second steps for double boosting; in the second predetermined period, a first step for triple boosting in which the charging portion applies the input voltage to the first capacitor, a second step for triple boosting in which the triple boosting portion applies the sum of the input voltage and the voltage across the first capacitor to the second capacitor, a third step for triple boosting in which the charging portion apply the input voltage to the first capacitor, and a fourth step for triple boosting in which the triple boosting portion applies the sum of the voltage across the first capacitor and the voltage across the second capacitor to the output capacitor and the third capacitor are repeated in that order. after the end of the second predetermined period, a first step for quadruple boosting in which the charging portion applies the input voltage to the first capacitor, a second step for quadruple boosting in which the quadruple boosting portion applies the sum of the input voltage and the voltage across the first capacitor to the second capacitor, a third step for quadruple boosting in which the charging portion apply the input voltage to the first capacitor, a fourth step for quadruple boosting in which the quadruple boosting portion applies the sum of the voltage across the first capacitor and the voltage across the second capacitor to the third capacitor, a fifth step for quadruple boosting in which the charging portion applies the input voltage to the first capacitor, and a sixth step for quadruple boosting in which the quadruple boosting portion applies the sum of the voltage across the first capacitor and a voltage across the third capacitor to the output capacitor are repeated in that order. 9. A boosting method for boosting an input voltage to a voltage three or higher integer times, the method comprising: a double boosting step of, in a first predetermined period after start of a boosting operation, applying the input voltage to a first capacitor and applying a sum of the input voltage and a voltage across the first capacitor to an output capacitor, while applying the input voltage to a second capacitor; and a triple boosting step of repeating in order, after end of the first predetermined period, a first application step of applying the input voltage to the first capacitor and applying a sum of the input voltage and the voltage across the first capacitor to the second capacitor and a second application step of applying the input voltage to the first capacitor and applying a sum of the voltage across the first capacitor and a voltage across the second capacitor to the output capacitor."
  ],
  "description_excerpt": "1. Field of the Invention\n\nThe present invention relates to a boosting circuit of charge pump type and a boosting method for boosting an input voltage to a voltage three or higher integer times.\n\n2. Description of the Related Background Art\n\nLiquid crystal displays need a voltage higher than a power supply voltage to drive a liquid crystal display panel. For reduction in size and weight, a boosting circuit of charge pump type for boosting the power supply voltage is incorporated into a semiconductor integrated circuit that comprises a drive circuit (see Japanese Patent Application Laid-Open No. 2004-64937).\n\nFIG. 1 shows the configuration of a conventional triple boosting circuit of charge pump type. The conventional boosting circuit has switch elements SW 1 A, SW 1 B, SW 2 A, SW 2 B, SW 3 A, and SW 3 B which are included in a semiconductor integrated circuit 1. The switch elements SW 1 A, SW 1 B, SW 2 A, SW 2 B, SW 3 A, and SW 3 B are on-off switches which are turned on/off by a not-shown controller. The semiconductor integrated circuit 1 has external component connection terminals A 1 to A 3, AC+, AC−, and AG. The switch elements SW 1 A and SW 2 B are each connected at one end to the connection terminal A. The switch elements SW 2 A and SW 3 B are each connected at one end to the connection terminal A 2. The switch element SW 3 A is connected at one end to the connection terminal A 3. The switch element SW 1 B is connected at one end to the connection terminal AG, the ground terminal. The other ends of the switch elements SW 1 A, SW 2 A, and SW 3 A are connected to the connection terminal AC+.",
  "cpc": [
    "H02M 3/07",
    "G05F 1/10",
    "G05F 3/02"
  ],
  "ipc": [
    "G05F 1/10",
    "H10D 84/00",
    "H10D 84/03",
    "G05F 3/02"
  ],
  "assignees": [
    "Oki Semiconductor Co Ltd"
  ],
  "inventors": [
    "Hiroaki Kawano"
  ],
  "filing_date": "2011-03-18",
  "publication_date": "2011-10-20",
  "priority_date": "2010-04-14",
  "application_number": "US-201113064324-A",
  "family_id": "44787792",
  "cited_by_count": 30,
  "citations": [
    "US6960955B2",
    "US7453711B2",
    "US7663427B2"
  ]
}