Providing Adaptive Frequency Control For A Processor

{
  "publication_number": "US2011047401A1",
  "country": "US",
  "kind": "A1",
  "title": "Providing Adaptive Frequency Control For A Processor",
  "abstract": "In one embodiment, the present invention includes a method for receiving utilization data from thread units of one or more processor cores, determining an operating frequency for a core clock signal based on the utilization data, a target utilization value, and an operating mode of the processor, and generating the core clock signal based on the determined operating frequency. Other embodiments are described and claimed.",
  "claims": [
    "1. An apparatus comprising: at least first and second thread units each to store an architectural state for a corresponding thread and to provide a first count value and a second count value to a controller, the first count value corresponding to a number of total clock cycles and the second count value corresponding to a number of active clock cycles; and the controller coupled to the at least first and second thread units to receive the first and second count values and to calculate a utilization value for each of the first and second thread units based thereon, and to determine a ratio used to set a core clock frequency based at least in part on the utilization values, a target utilization value, and a current ratio. 2. The apparatus of claim 1, further comprising a core clock generator to receive the ratio and a reference clock and to generate the core clock at the core clock frequency and to provide the core clock to a plurality of cores each including the at least first and second thread units. 3. The apparatus of claim 2, wherein the at least first and second thread units are to provide the first and second count values at a periodic interval. 4. The apparatus of claim 1, wherein the target utilization value is at least 90%. 5. The apparatus of claim 1, wherein the controller is to calculate the utilization value based on the first and second count values. 6. The apparatus of claim 5, wherein the controller is to receive the first and second count values from the at least first and second units of a plurality of cores and to calculate the utilization value for each thread unit of each core. 7. The apparatus of claim 6, wherein the controller is to determine the ratio based on less than all of the calculated utilization values. 8. The apparatus of claim 6, wherein the controller is to determine the ratio based on a weighted value for each of the calculated utilization values. 9. The apparatus of claim 1, wherein the controller is to determine the ratio independently of an operating system (OS) power management mechanism and wherein the controller is transparent to the OS. 10. A method comprising: receiving utilization data from at least a first thread unit and a second thread unit of a first processor core; determining an operating frequency for a core clock signal based on the utilization data, a target utilization value, and an operating mode of a processor including the first processor core; and generating the core clock signal based on the determined operating frequency. 11. The method of claim 10, wherein the utilization data comprises a first count value corresponding to a number of total clock cycles and a second count value corresponding to a number of active clock cycles. 12. The method of claim 10, further comprising receiving the utilization data from a plurality of processor cores each including a first thread unit and a second thread unit and determining the operating frequency based on the utilization data from the plurality of processor cores. 13. The method of claim 12, wherein determining the operating frequency includes performing a weighting of the calculated utilization values for each of the first and second threads of each of the plurality of processor cores. 14. The method of claim 11, further comprising calculating a utilization value for each of the first and second thread units based on the first and second count values. 15. The method of claim 10, further comprising receiving the utilization data from a performance monitor unit of the first processor core. 16. A system comprising: a processor including a plurality of cores each having a plurality of thread units each to store an architectural state for a corresponding thread and to output a first count value and a second count value, a logic coupled to the plurality of cores to receive the first and second count values and to calculate a utilization value for each of the plurality of thread units of the plurality of cores based thereon, and to determine a ratio used to set a core clock frequency based on the utilization values, a target utilization value for the processor, and a current ratio of the processor; and a dynamic random access memory (DRAM) coupled to the processor. 17. The system of claim 16, wherein the processor further comprises a clock controller coupled to the logic to receive the ratio and a reference clock and to generate the core clock at the core clock frequency and to provide the core clock to the plurality of cores. 18. The system of claim 17, wherein the logic is to determine the ratio according to: U C *R C /U C +S (U T −U C)), where U C is a current utilization value calculated from the utilization values of the plurality of threads of the plurality of cores, R C is the current ratio, U T is the target utilization value, and S is a slope value. 19. The system of claim 16, wherein the logic is to perform a statistical weighting of the utilization values for each of the thread units of each of the plurality of cores. 20. The system of claim 19, wherein the statistical weighting is an exponential weighting."
  ],
  "cpc": [
    "G06F 1/324",
    "G06F 1/08",
    "G06F 1/3203",
    "Y02D 10/00"
  ],
  "assignees": [
    "WERNER JAMES B"
  ],
  "filing_date": "2009-08-24",
  "publication_date": "2011-02-24",
  "priority_date": "2009-08-24",
  "application_number": "US-54593709-A",
  "family_id": "43606243",
  "citations": [
    "US2002007463A1",
    "US2004168170A1",
    "US2004216113A1",
    "US2005034002A1",
    "US2005132238A1",
    "US2005138442A1",
    "US2006031691A1",
    "US2008082844A1",
    "US2008172565A1",
    "US2008201591A1",
    "US2009049314A1",
    "US2009150695A1",
    "US2009150696A1",
    "US2009172424A1",
    "US2009199019A1",
    "US2010031266A1",
    "US2010037038A1",
    "US2010146316A1",
    "US2010191936A1",
    "US2010218029A1",
    "US2010332856A1",
    "US2011197195A1",
    "US5590342A",
    "US6480966B1",
    "US6711447B1",
    "US6711526B2",
    "US6829713B2",
    "US7146514B2",
    "US7770034B2",
    "US7861102B1",
    "US7925901B2",
    "US8020020B2"
  ]
}