ATM cell switching system

{
  "publication_number": "US6463057B1",
  "country": "US",
  "kind": "B1",
  "title": "ATM cell switching system",
  "abstract": "An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.",
  "claims": [
    "1. A band control method of a packet switching system including a buffer memory for storing fixed-length packets, an idle address memory for storing information corresponding to idle addresses of said buffer memory, and a control circuit for controlling said buffer memory and said idle address memory based on identifiers of said fixed-length packets, and which switches fixed-length packets input from a plurality of input lines into any lines of a plurality of output lines, comprising the steps of: temporarily storing information from said idle address memory for each of said identifiers when fixed-length packets are stored in said buffer memory based on said information from said idle address memory; designating an order of outputting fixed-length packets to said output lines for each of said identifiers of said fixed-length packets; and reading information stored temporarily in said order in accordance with said identifiers for each of said identifiers, reading fixed-length packets from said buffer memory in accordance with said information and storing said information to said idle address memory.",
    "2. A band control method according to claim 1, wherein said step of designating an order of outputting fixed-length packets to said output lines for each of said identifiers of said fixed-length packets comprises steps of: selecting said output lines in accordance with a preset order; and designating the output order for each identifier of fixed-length packets in said selected output lines.",
    "3. A band control method according to claim 1, wherein in said step of designating an order of outputting fixed-length packets to said output lines for each of said identifiers of said fixed-length packets, fixed-length packets having different identifiers are set to be successively output to said output lines.",
    "4. A band control method of a packet switching system according to claim 1, wherein each of said identifiers is a virtual path identifier or a virtual channel identifier or both thereof.",
    "5. A band control circuit including a buffer memory for storing fixed-length packets, an idle address memory for storing information corresponding to idle addresses of said buffer memory, and a control circuit for controlling of writing and reading of said buffer memory and idle address memory on the basis of identifiers of said fixed-length packets, and which switches fixed-length packets input from a plurality of input lines into any lines of a plurality of output lines, comprising: a table for temporarily storing information from said idle address memory used for reading fixed-length packets from said buffer memory for each of said identifiers; a scheduler for designating an identifier of fixed-length packets to be output; and a circuit for outputting information read out from said table in accordance with the identifier output by said scheduler as a reading address of said buffer memory and storing said information to said idle address memory.",
    "6. A band control circuit of a packet switching system including a buffer memory for storing fixed-length packets, an idle address memory for storing information corresponding to idle addresses of said buffer memory, and a control circuit for controlling of writing and reading of said buffer memory and said idle address memory based on identifiers of said fixed-length packets, and which switches fixed-length packets input from a plurality of input lines into any lines of a plurality of output lines, comprising: a first table for temporarily storing information from said idle address memory used for reading fixed-length packets from said buffer memory for each of said identifiers; a first counter for designating a line for outputting fixed-length packets; a second counter for designating an order of fixed-length packets to be output to said output line; a second table for designating an identifier of said identifiers of said fixed-length packets to be output to said output line from said second counter; and a circuit for outputting information read out from said first table in accordance with the identifier output by said second table as a reading address of said buffer memory and for storing said information to said idle address memory.",
    "7. A band control method of a packet switching system according to claim 2, wherein each of said identifiers is a virtual path identifier or a virtual channel identifier or both thereof."
  ],
  "description_excerpt": "The present invention relates to a switching system, or more in particular to an ATM (Asynchronous Transfer Mode) switching system used with the speech path equipment of a wide-bandwidth ISDN exchange and, especially, an ATM switching system suitable for accommodating a plurality of types of input-output links having different transmission rates.\n\nA “TDM Switching System” proposed by JP-A-59-135994 is known, for example, as an ATM switching system applied to the wide-bandwidth ISDN exchange.\n\nThis switching system comprises a multiplexer for multiplexing a fixed-length packet (hereinafter referred to as “the cell”) inputted from each input line, a buffer memory for inputting a multiplexed cell, a demultiplexer for periodically separating the cells outputted from the buffer memory among output lines, and a buffer memory control circuit for controlling the buffer memory for each output line. The buffer memory control circuit, which includes FIFO (First In First Out) memories corresponding to the output lines, inputs a write address for the buffer memory into a FIFO memory corresponding to the cell output destination judged from the header information of a cell when the cell is written into the buffer memory. Also, the cell output from the buffer memory corresponding to each output line is produced at predetermined time intervals so that a read address is outputted to the buffer memory from the FIFO memory corresponding to each output line in timing with the cell output.\n\nAccording to the above-mentioned prior art, the reading of a cell from the buffer memory is controlled to a predetermined timing for each output line.",
  "cpc": [
    "H04L 12/5601",
    "H04J 3/247",
    "H04L 12/5602",
    "H04L 2012/5627",
    "H04L 2012/5631",
    "H04L 2012/5638",
    "H04L 2012/5649",
    "H04L 2012/565",
    "H04L 2012/5651",
    "H04L 2012/5652",
    "H04L 2012/5672",
    "H04L 2012/5679",
    "H04L 2012/568",
    "H04L 2012/5681",
    "H04L 2012/5682",
    "H04L 45/04",
    "H04L 49/108",
    "H04L 49/203",
    "H04L 49/255",
    "H04L 49/256",
    "H04L 49/3081",
    "H04Q 11/0478"
  ],
  "ipc": [
    "H04J 3/24",
    "H04L 12/56",
    "H04Q 11/04"
  ],
  "assignees": [
    "Hitachi Ltd"
  ],
  "inventors": [
    "Takahiko Kozaki",
    "Junichirou Yanagi",
    "Kiyoshi Aiki",
    "Yutaka Ito",
    "Kaoru Aoki",
    "Shinobu Gohara"
  ],
  "filing_date": "2000-11-20",
  "publication_date": "2002-10-08",
  "grant_date": "2002-10-08",
  "priority_date": "1987-07-15",
  "application_number": "US-71494700-A",
  "family_id": "26377630",
  "cited_by_count": 10,
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}