Phase correction circuit for radio communication apparatus

{
  "publication_number": "US6721370B1",
  "country": "US",
  "kind": "B1",
  "title": "Phase correction circuit for radio communication apparatus",
  "abstract": "A phase correction circuit for a radio communication apparatus includes a variable gain amplifier and phase correction unit. The variable gain amplifier amplifies a transmission/reception signal on the basis of a gain variably set in accordance with a gain signal. The phase correction unit has a phase characteristic opposite to that of the variable gain amplifier, corrects the phase of the transmission/reception signal on the basis of the gain signal supplied to the variable gain amplifier, and cancels a phase change of the signal caused in the variable gain amplifier.",
  "claims": [
    "1. A phase correction circuit for a radio communication apparatus, comprising: a variable gain amplifier for amplifying a reception signal on the basis of a gain variably set in accordance with a gain control signal; demodulation means for demodulating the amplified reception signal (outputted from said variable gain amplifier) into I and Q components on an I-Q plane; A/D conversion means for converting the I and Q components output from said demodulation means into digital signals; and phase correction means, having a phase characteristic opposite to a phase characteristic of said variable gain amplifier, for increasing/decreasing the digital I and Q components output from said A/D conversion means on the basis of the gain control signal supplied to said variable gain amplifier, and canceling a phase change of the reception signal caused by said variable gain amplifier.",
    "2. A phase correction circuit for a radio communication apparatus, comprising: a variable gain amplifier for amplifying a transmission signal on the basis of a gain variably set in accordance with a gain control signal; D/A conversion means for converting digital I and Q components on an I-Q plane into analog signals; modulation means for modulating the analog I and Q components output from said D/A conversion means, and outputting the modulated I and Q components as the transmission signal to said variable gain amplifier; and phase correction means, having a phase characteristic opposite to a phase characteristic of said variable gain amplifier, for increasing/decreasing the digital I and Q components output to said D/A conversion means on the basis of the gain control signal supplied to said variable gain amplifier, and canceling a phase change of the transmission signal (outputted from said variable gain amplifier) caused by said variable gain amplifier."
  ],
  "description_excerpt": "The present invention relates to a phase correction circuit for a radio communication apparatus and, more particularly, to a phase correction circuit for a radio communication apparatus that has a variable gain amplifier for amplifying a reception signal or transmission signal.\n\nAccording to a conventional phase shift keying scheme such as a CDMA (Code Division Multiple Access) radio scheme used in digital radio communication systems, data is transmitted in correspondence with each phase of a carrier wave. For example, in a QPSK (Quadrature Phase Shift Keying) scheme, as shown in FIG. 6A, data “ 00 ”, “ 10 ”, “ 11 ”, and “ 01 ” are transmitted while being assigned as symbols on the I-Q plane to π/4, 3π/4, 5π/4, and 7π/4 phases, respectively.\n\nIn this case, the respective data shift from each other by a π/4 phase. While holding the phase differences between the respective symbols, only the entire phase, i.e., reference phase can be rotated by φ, as shown in FIG. 6 B. In interpolation synchronous detection used in this phase shift keying scheme, the reference phase is rotated for each slot set in a main signal, and rotated for each data in the slot.\n\nFIGS. 7A and 7B show an example of the signal format according to the interpolation synchronous detection scheme, and FIGS. 8A and 8B show a phase change in the interpolation synchronous detection scheme.\n\nIn FIG. 7A, respective slots include PILOT portions P 1 to P 3 each representing the reference phase of a corresponding slot, and DATA portions D 1 to D 3 each representing transmission data.",
  "cpc": [
    "H03F 1/3247",
    "H03G 3/30"
  ],
  "ipc": [
    "H03F 1/32",
    "H03G 3/30",
    "H04B 1/707",
    "H04J 13/00",
    "H04L 27/20",
    "H04L 27/22"
  ],
  "assignees": [
    "NEC Corp"
  ],
  "inventors": [
    "Kazuhiro Kurihara"
  ],
  "filing_date": "1999-10-20",
  "publication_date": "2004-04-13",
  "grant_date": "2004-04-13",
  "priority_date": "1998-10-21",
  "application_number": "US-42185199-A",
  "family_id": "17873901",
  "cited_by_count": 14,
  "citations": [
    "GB559093A",
    "US4700151A",
    "US5093637A",
    "GB2240893A",
    "US5142240A",
    "JPH03289220A",
    "GB2243736A",
    "JPH0423524A",
    "EP0839606A2",
    "JPH0575541A",
    "JPH05183359A",
    "US5509030A",
    "JP3289220B2",
    "JPH0865352A",
    "JPH08102768A",
    "JPH08330868A",
    "WO1997028598A1",
    "JPH09247228A",
    "US5787362A",
    "US6373902B1",
    "US6587513B1"
  ]
}