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Patent · US9344042B2 · B2 · US

High efficiency power amplifiers with advanced power solutions

(11) Publication number
US9344042B2
(21) Application number
14/185,885
(22) Filing date
2014-02-20
(30) Priority date
2013-02-27
(43) Publication date
2016-05-17
(45) Date of grant
2016-05-17
(51) IPC
H03F 3/19; H03F 3/21; H03F 1/02; H03F 1/32; H03F 1/56; H03F 3/195; H03F 3/24; H03F 3/45
(52) CPC
  • H03F Amplifiers: 1/0222, 1/025, 1/32, 1/56, 2200/102, 2200/15, 2200/387, 2200/541, 3/195, 3/245
  • H02M Apparatus for conversion between AC and AC, between AC and DC, or between DC and DC, and for use with mains or similar power supply systems; conversion of DC or AC input power into surge output power; control or regulation thereof: 1/0074, 7/483
(72) Inventors
Hengchun Mao
(54) Title
High efficiency power amplifiers with advanced power solutions
(57) Abstract

A device comprises a switch network having a plurality of switch cells connected in series, an output voltage at an output voltage port with an output capacitor, and an impedance network coupled between the switch network and an output voltage port with an output capacitor. Each switch cell has a plurality of input voltages and a plurality of switches, in which each switch is coupled to an input voltage, and a first input voltage coupled to a first switch has a different value from a second input voltage coupled to a second switch. The output voltage is configured to be a combination of the input voltages of the switch network in the form of: Vo=Σ 1 N Ki×Vi, where Vo is the output voltage, N is the number of input voltages, Vi is the ith input voltage, and Ki is an integer equal to 0 or 1 depending on the ON/OFF status of the switches in the switch network.

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Claims (14)

  1. A device comprising: a switch network having a plurality of switch cells connected in series, wherein each switch cell has a plurality of input voltages and a plurality of switches, wherein each switch is coupled to an input voltage, and wherein a first input voltage coupled to a first switch has a different value from a second input voltage coupled to a second switch; an output voltage at an output voltage port with an output capacitor; and an impedance network coupled between the switch network and an output voltage port, wherein the output voltage is configured to be a combination of the input voltages of the switch network in the form of: Vo=Σ 1 N Ki×Vi, wherein Vo is the output voltage, N is the number of input voltages, Vi is the ith input voltage, and Ki is an integer equal to 0 or 1 depending on the ON/OFF status of the switches in the switch network.
  2. The device of claim 1, wherein the switch network has a 2-switch cell which comprises 2 switches arranged in totem pole and is coupled to an input voltage.
  3. The device of claim 1, wherein the switch network has a 4-switch cell which comprises 4 switches arranged in two pairs and coupled to two input voltages V1 and V2, wherein each pair has 2 switches and is coupled to an input voltage, and wherein V1 has a different value from V2.
  4. The device of claim 3, wherein the input voltages have a substantially doubling relationship: V2=2V1.
  5. The device of claim 1, wherein a plurality of gate drive signals of the switches are controlled by a decoding process.
  6. The device of claim 1, wherein the impedance network has an inductor.
  7. The device of claim 6, wherein the inductor comprises a parasitic inductance of a current path between a plurality of the switches in the switch cells and the output voltage port.
  8. The device of claim 6, wherein the inductor and the output capacitor are part of a resonant tank having a quality factor close to 1.
  9. The device of claim 1, wherein the switch network is configured such that an N1-switch cell and an N2-switch cell are in series, and the switch network is capable of producing N1×N2 voltage levels at the output voltage port, where N1 and N2 are positive integers representing the number of switches in the switch cells correspondingly.
  10. The device of claim 1, wherein the switch network comprises a first switch cell and a second switch cell, wherein an input voltage in the first switch cell is twice the value of an input voltage in the second switch cell.
  11. The device of claim 1, wherein a switch cell is integrated into a single package.
  12. The device of claim 1, wherein the switch network is integrated into a single package.
  13. The device of claim 1, wherein the device is integrated into a single package.
  14. The device of claim 1, wherein the device is integrated with a power amplifier in a single package.

Description

The present invention relates to power conversion and power amplifiers, and, in particular embodiments, to high efficiency power topologies and control suitable for high efficiency power amplifiers and other demanding applications.

Power amplifiers are widely used in wireless communication systems and other electronic devices, especially in mobile devices. To achieve high system efficiency and/or longer battery life, it is very important to maintain high efficiency in power amplifiers.

The power amplifiers in many systems see signals with high peak to average power ratio. Because a typical power amplifier gets its energy from a power supply coupled to the drain (or the collector if a transistor is used) of its main power switch (a MOSFET or a transistor), its power efficiency can be improved by changing the drain voltage of its main power switch through changing the voltage of its drain power supply according to the envelope of the signal being processed by the power amplifier. When the signal envelope has high bandwidth as often seen in today's wireless systems, changing the voltage of drain power supply may cause the output signal of the power amplifier to be distorted.

Moreover, as the bandwidth of the signal increases, the power supply's control bandwidth should be increased accordingly. This put very high burden into the power supply, and the efficiency of the power supply is low with existing technology.

Improvements are needed to reduce the signal distortion in a power amplifier with variable drain voltage, and to increase the efficiency of the drain power supply.

Citations (3)

  • US6031746A
  • US7050311B2
  • US8149599B2
Record as JSON
{
  "publication_number": "US9344042B2",
  "country": "US",
  "kind": "B2",
  "title": "High efficiency power amplifiers with advanced power solutions",
  "abstract": "A device comprises a switch network having a plurality of switch cells connected in series, an output voltage at an output voltage port with an output capacitor, and an impedance network coupled between the switch network and an output voltage port with an output capacitor. Each switch cell has a plurality of input voltages and a plurality of switches, in which each switch is coupled to an input voltage, and a first input voltage coupled to a first switch has a different value from a second input voltage coupled to a second switch. The output voltage is configured to be a combination of the input voltages of the switch network in the form of: Vo=Σ 1 N Ki×Vi, where Vo is the output voltage, N is the number of input voltages, Vi is the ith input voltage, and Ki is an integer equal to 0 or 1 depending on the ON/OFF status of the switches in the switch network.",
  "claims": [
    "1. A device comprising: a switch network having a plurality of switch cells connected in series, wherein each switch cell has a plurality of input voltages and a plurality of switches, wherein each switch is coupled to an input voltage, and wherein a first input voltage coupled to a first switch has a different value from a second input voltage coupled to a second switch; an output voltage at an output voltage port with an output capacitor; and an impedance network coupled between the switch network and an output voltage port, wherein the output voltage is configured to be a combination of the input voltages of the switch network in the form of: Vo=Σ 1 N Ki×Vi, wherein Vo is the output voltage, N is the number of input voltages, Vi is the ith input voltage, and Ki is an integer equal to 0 or 1 depending on the ON/OFF status of the switches in the switch network.",
    "2. The device of claim 1, wherein the switch network has a 2-switch cell which comprises 2 switches arranged in totem pole and is coupled to an input voltage.",
    "3. The device of claim 1, wherein the switch network has a 4-switch cell which comprises 4 switches arranged in two pairs and coupled to two input voltages V1 and V2, wherein each pair has 2 switches and is coupled to an input voltage, and wherein V1 has a different value from V2.",
    "4. The device of claim 3, wherein the input voltages have a substantially doubling relationship: V2=2V1.",
    "5. The device of claim 1, wherein a plurality of gate drive signals of the switches are controlled by a decoding process.",
    "6. The device of claim 1, wherein the impedance network has an inductor.",
    "7. The device of claim 6, wherein the inductor comprises a parasitic inductance of a current path between a plurality of the switches in the switch cells and the output voltage port.",
    "8. The device of claim 6, wherein the inductor and the output capacitor are part of a resonant tank having a quality factor close to 1.",
    "9. The device of claim 1, wherein the switch network is configured such that an N1-switch cell and an N2-switch cell are in series, and the switch network is capable of producing N1×N2 voltage levels at the output voltage port, where N1 and N2 are positive integers representing the number of switches in the switch cells correspondingly.",
    "10. The device of claim 1, wherein the switch network comprises a first switch cell and a second switch cell, wherein an input voltage in the first switch cell is twice the value of an input voltage in the second switch cell.",
    "11. The device of claim 1, wherein a switch cell is integrated into a single package.",
    "12. The device of claim 1, wherein the switch network is integrated into a single package.",
    "13. The device of claim 1, wherein the device is integrated into a single package.",
    "14. The device of claim 1, wherein the device is integrated with a power amplifier in a single package."
  ],
  "description_excerpt": "The present invention relates to power conversion and power amplifiers, and, in particular embodiments, to high efficiency power topologies and control suitable for high efficiency power amplifiers and other demanding applications.\n\nPower amplifiers are widely used in wireless communication systems and other electronic devices, especially in mobile devices. To achieve high system efficiency and/or longer battery life, it is very important to maintain high efficiency in power amplifiers.\n\nThe power amplifiers in many systems see signals with high peak to average power ratio. Because a typical power amplifier gets its energy from a power supply coupled to the drain (or the collector if a transistor is used) of its main power switch (a MOSFET or a transistor), its power efficiency can be improved by changing the drain voltage of its main power switch through changing the voltage of its drain power supply according to the envelope of the signal being processed by the power amplifier. When the signal envelope has high bandwidth as often seen in today's wireless systems, changing the voltage of drain power supply may cause the output signal of the power amplifier to be distorted.\n\nMoreover, as the bandwidth of the signal increases, the power supply's control bandwidth should be increased accordingly. This put very high burden into the power supply, and the efficiency of the power supply is low with existing technology.\n\nImprovements are needed to reduce the signal distortion in a power amplifier with variable drain voltage, and to increase the efficiency of the drain power supply.",
  "cpc": [
    "H03F 1/0222",
    "H02M 1/0074",
    "H02M 7/483",
    "H03F 1/025",
    "H03F 1/32",
    "H03F 1/56",
    "H03F 2200/102",
    "H03F 2200/15",
    "H03F 2200/387",
    "H03F 2200/541",
    "H03F 3/195",
    "H03F 3/245"
  ],
  "ipc": [
    "H03F 3/19",
    "H03F 3/21",
    "H03F 1/02",
    "H03F 1/32",
    "H03F 1/56",
    "H03F 3/195",
    "H03F 3/24",
    "H03F 3/45"
  ],
  "inventors": [
    "Hengchun Mao"
  ],
  "filing_date": "2014-02-20",
  "publication_date": "2016-05-17",
  "grant_date": "2016-05-17",
  "priority_date": "2013-02-27",
  "application_number": "US-201414185885-A",
  "family_id": "51387542",
  "cited_by_count": 29,
  "citations": [
    "US6031746A",
    "US7050311B2",
    "US8149599B2"
  ]
}

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