Frequency synthesizing apparatus and method having injection-locked quadrature VCO in RF transceiver

{
  "publication_number": "US7656238B2",
  "country": "US",
  "kind": "B2",
  "title": "Frequency synthesizing apparatus and method having injection-locked quadrature VCO in RF transceiver",
  "abstract": "A frequency synthesizing apparatus and method having an injection-locked quadrature VCO in an RF transceiver is provided. In the frequency synthesizer, an I signal following a frequency of a high frequency signal that is input using the injection-locked quadrature VCO and a Q signal thereof are simultaneously generated to have an appropriate driving power. Accordingly, the I signal and the Q signal thereof that are generated in the injection-locked quadrature VCO may be utilized as a local signal for frequency up/down-conversion, without being buffered. An output of an SSB mixer may be directly input into the injection-locked quadrature VCO. Also, high frequency signals that are generated in another circuit such as the SSB mixer, a PLL, or a VCO may be selected to be input into the injection-locked quadrature VCO by a selector.",
  "claims": [
    "1. A frequency synthesizer comprising: a mixer which generates a frequency synthesized signal whose frequency is a synthesis of first high frequency I and Q signals and second high frequency I and Q signals; a selector which selects and outputs one of the I signal of the first high frequency and the frequency synthesized signal; and an oscillator which receives an output signal of the selector and generates a first local signal and a second local signal having a quadrature-phase with each other based on the output signal of the selector.",
    "2. The frequency synthesizer of claim 1, wherein each of the first and second local signal has a frequency identical to a frequency of the output signal of the selector.",
    "3. The frequency synthesizer of claim 1, wherein the first and second local signal of the oscillator each has a frequency which is one half a frequency of the output signal of the selector.",
    "4. The frequency synthesizer of claim 1, wherein the frequency synthesized signal is an addition of the first high frequency I and Q signals and the second high frequency I and Q signals.",
    "5. The frequency synthesizer of claim 1, wherein the frequency synthesized signal is a difference between the first high frequency I and Q signals and the second high frequency I and Q signals.",
    "6. The frequency synthesizer of claim 1, wherein the oscillator comprises: a first oscillator which generates a first differential signal set from a second differential signal set input via first positive and negative input terminals; and a second oscillator which receives positive and negative signals of a third differential signal set for frequency locking via second positive and negative input terminals, respectively, receives positive and negative signals of the first differential signal set via third positive and negative input terminals, respectively, and generates the second differential signal set based on the positive and negative signals of the third differential signal set and the positive and negative signals of the first differential signal set.",
    "7. The frequency synthesizer of claim 6, wherein the positive signal of the second differential signal is input to the first negative input terminal of the first oscillator, and the negative signal of the second differential signal is input to the first positive input terminal of the first oscillator.",
    "8. The frequency synthesizer of claim 7, wherein: the first oscillator comprises a plurality of metal-oxide semiconductor field effect transistors (MOSFETs) having gate terminals coupled between a first load circuit and a first current source, as the first positive and negative input terminals, and the second oscillator comprises a plurality of MOSFETs having gate terminals coupled between second load circuit and second current source, as the second positive and negative input terminals and the third positive and negative input terminals.",
    "9. A frequency synthesizing method comprising: generating a frequency synthesized signal whose frequency is a synthesis of first high frequency I and Q signals and second high frequency I and Q signals; selecting one of the first high frequency I signal and the frequency synthesized signal and outputting a selected signal; inputting the selected signal into an oscillator; and generating a first local signal and a second local signal having a quadrature-phase with each other based on the selected signal.",
    "10. The frequency synthesizing method of claim 9, wherein each of the first and second local signal has a frequency identical to a frequency of the selected signal.",
    "11. The frequency synthesizing method of claim 9, wherein the first and second local signal each has a frequency which is one half a frequency of the selected signal.",
    "12. The frequency synthesizing method of claim 9, wherein the frequency synthesized signal is an addition of the first high frequency I and Q signals and the second high frequency I and Q signals.",
    "13. The frequency synthesizing method of claim 9, wherein the frequency synthesized signal is a difference between the first high frequency I and Q signals and the second high frequency I and Q signals.",
    "14. The frequency synthesizing method of claim 9, wherein the generating the first local signal and the second local signal comprises: generating at a first oscillator a first differential signal set using a second differential signal set input via first positive and negative input terminals of the first oscillator; receiving at a second oscillator positive and negative signals of a third differential signal set for frequency locking via second positive and negative input terminals of the second oscillator, respectively; receiving at the second oscillator positive and negative signals of the first differential signal set via third positive and negative input terminals of the second oscillator, respectively; and generating at the second oscillator a second differential signal set.",
    "15. The frequency synthesizing method of claim 14, wherein a positive signal of the second differential signal is input to the first negative input terminal of the first oscillator, and a negative signal of the second differential signal is input to the first positive input terminal of the first oscillator."
  ],
  "description_excerpt": "1. Field of the Invention The present invention relates to a frequency synthesizing apparatus for a radio frequency (RF) transceiver, and more particularly, to a frequency synthesizing apparatus and method which can reduce a circuit area and may be low powered, and also can reduce signal distortion. 2. Description of Related Art A frequency synthesizer generating a local oscillation (LO) signal or an LO generation block is required in a system for transmitting/receiving wireless data, such as a mobile phone, a digital multimedia broadcasting (DMB) phone, and a personal digital assistant (PDA). In this instance, an LO signal is required in a mixer of a transceiver to up/down-convert a frequency of a transmitted/received signal. As an example, a frequency synthesizer is utilized to down-convert a received RF signal into a baseband signal or to up-convert a baseband signal into a carrier signal, in a Code Division Multiple Access (CDMA) system, a global positioning system (GPS), a personal communication system (PCS), an International Mobile Telecommunication (IMT) 2000 system, Wireless Broadband Internet (WiBro) system, a wireless local area network (WLAN) system, an Ultra Wideband (UWB) system, and a WiMax system for a ubiquitous system.\n\nFIG. 1 is a diagram illustrating a related frequency synthesizer 100 generating two high frequency signals having a different phase from each other. Referring to FIG. 1, the frequency synthesizer 100 includes two single side band (SSB) mixers 110 and 120, a selector 130 and a buffer 140.",
  "cpc": [
    "H03L 7/24",
    "B60J 5/0493",
    "B60J 5/062",
    "B60Y 2200/30",
    "B61D 19/005",
    "E05Y 2900/51",
    "F16B 5/02",
    "H03B 21/02",
    "H03L 7/0995"
  ],
  "ipc": [
    "H03B 21/01",
    "H03L 7/00"
  ],
  "assignees": [
    "SAMSUNG ELECTRONICS CO LTD"
  ],
  "inventors": [
    "SUH CHUN DEOK",
    "KOH JEONG WOOK",
    "KIM HOON TAE"
  ],
  "filing_date": "2006-06-07",
  "publication_date": "2010-02-02",
  "grant_date": "2010-02-02",
  "priority_date": "2006-01-06",
  "application_number": "US-44788706-A",
  "family_id": "38232248",
  "citations": [
    "JPS57125528A",
    "KR20020006155A",
    "KR20050008463A",
    "KR20050008464A",
    "US5343168A",
    "US6175285B1",
    "US6960962B2"
  ]
}