Numerically-controlled phase-lock loop with input timing reference-dependent ratio adjustment

{
  "publication_number": "US7746972B1",
  "country": "US",
  "kind": "B1",
  "title": "Numerically-controlled phase-lock loop with input timing reference-dependent ratio adjustment",
  "abstract": "A numerically-controlled phase-lock loop with input clock dependent ratio adjustment provides for narrower-bandwidth loops that lock to a wide range of frequencies and/or operation with an absent or degraded input timing reference. A timing reference characteristic detector determines an input frequency range of the input timing reference signal, the data type of the timing reference, and/or whether a timing reference signal of sufficient quality is present. A numerically controlled oscillator is controlled by a numeric ratio that is adjusted to provide the desired clock frequency output in conformity with the detected frequency range and/or data type. If the timing reference signal is absent or degraded, then the numeric ratio can be set to a fixed value or a local timing reference can be applied in order to generate the desired clock output frequency.",
  "claims": [
    "1. A circuit for providing a clock output synchronized to a timing reference signal supplied to a timing reference input, said circuit comprising: a numerically-controlled oscillator for providing said clock output and having an input for receiving a rational numeric representation of a ratio between a frequency of said clock output and a frequency of a stable clock for controlling said frequency of said clock output; a digital phase-frequency detector for generating a representation of an on-going phase-frequency difference between said timing reference signal and a signal derived from said clock output; a digital loop filter for filtering said representation of said on-going phase-frequency difference to provide said rational numeric representation to said numerically-controlled oscillator; a timing reference characteristic detection circuit for detecting a characteristic of the timing reference signal independent of the on-going phase-frequency difference; and a ratio adjustment circuit for adjusting said rational numeric representation resulting from the filtered representation of the on-going phase-frequency difference in conformity with said detected characteristic.",
    "2. The circuit of claim 1, wherein said timing reference characteristic detector detects a frequency range of said timing reference signal, and wherein said ratio adjustment circuit adjusts said rational numeric representation in conformity with said detected frequency range.",
    "3. The circuit of claim 2, wherein said timing reference signal has a frequency supplied from among a set of frequencies related by factors of two, and wherein said ratio adjustment circuit adjusts said rational numeric representation by shifting bits of said rational numeric representation according to a particular one of said factors of two determined in conformity with an output of said timing reference characteristic detector.",
    "4. The circuit of claim 1, wherein said timing reference characteristic detector detects absence of said timing reference signal, and wherein said ratio adjustment circuit selects a fixed ratio as said rational numeric representation in response to said detected absence.",
    "5. The circuit of claim 1, wherein said timing reference characteristic detector detects an absence of said timing reference signal and selects a local reference clock in place of said timing reference signal as an input to said phase/frequency detector and wherein said ratio adjustment circuit adjusts said rational numeric representation in conformity with a predetermined frequency of said local reference clock.",
    "6. The circuit of claim 1, wherein said timing reference characteristic detector detects a data type of said timing reference signal, and wherein said ratio adjustment circuit adjusts said rational numeric representation in conformity with said detected data type.",
    "7. The circuit of claim 1, wherein said stable clock is derived from said timing reference signal, whereby said numerically-controlled oscillator generates said clock output without requiring a locally generated clock.",
    "8. The circuit of claim 1, wherein said numerically-controlled oscillator is a direct digital synthesis circuit, comprising: a phase integrator for integrating said rational numeric representation at each period of said stable clock to generate a phase index; a sinusoid generating circuit for providing a digital representation of said at least one substantially sinusoidal analog signal in response to said phase index; a conversion circuit for converting said digital representation of said at least one substantially sinusoidal analog signal to said at least one substantially sinusoidal analog signal; and an analog-to-digital clock conversion circuit for converting an output of said conversion circuit to said clock output.",
    "9. The circuit of claim 1, wherein said numerically-controlled oscillator is a fractional-N oscillator circuit, comprising: a voltage controlled oscillator for providing said clock output; a local divider for dividing said clock output in conformity with a divisor input; a local phase-frequency detector for comparing an output of said local divider with said stable clock; an analog loop filter for filtering an output of said local phase-frequency detector to provide a control input of said voltage controlled oscillator; and a delta-sigma modulator having an input coupled to an output of said local phase-frequency detector and an output providing said divisor input of said local divider.",
    "10. A method of providing a clock output synchronized to a timing reference signal supplied to a timing reference input, said method comprising: generating a clock output from a numerically-controlled oscillator ratiometrically locked to a stable clock source, wherein a frequency of said clock output is controlled by a rational numeric representation of a ratio between a frequency of said clock output and a frequency of said stable clock; generating a representation of an on-going phase-frequency difference between said timing reference signal and a signal derived from said clock output; filtering said representation of said on-going phase-frequency difference with a digital filter to provide said rational numeric representation to said numerically-controlled analog oscillator; detecting a characteristic of said timing reference signal independent of said on-going phase-frequency difference; and adjusting said rational numeric representation resulting from the filtering of the representation of the on-going phase-frequency difference in conformity with said detected characteristic.",
    "11. The method of claim 10, wherein said detecting detects a frequency range of said timing reference signal, and wherein said adjusting adjusts said rational numeric representation in conformity with said detected frequency range.",
    "12. The method of claim 11, wherein said timing reference signal has a frequency supplied from among a set of frequencies related by factors of two, and wherein said adjusting adjusts said rational numeric representation by shifting bits of said rational numeric representation according to a particular one of said factors of two determined in conformity with a result of said detecting.",
    "13. The method of claim 10, wherein said detecting detects absence of said timing reference signal, and wherein said adjusting selects a fixed ratio as said rational numeric representation in response to said detecting absence.",
    "14. The method of claim 10, wherein said detecting detects absence of said timing reference signal, and further comprising in response to said detecting absence, selecting a local reference clock in place of said timing reference signal as input to said detecting, and wherein adjusting adjusts said rational numeric representation in conformity with a predetermined frequency of said local reference clock.",
    "15. The method of claim 10, wherein said detecting detects a data type of said timing reference signal, and wherein said adjusting adjusts said rational numeric representation in conformity with said detected data type.",
    "16. The method of claim 10, wherein said stable clock is derived from said timing reference signal, whereby said generating a clock output generates said clock output without using a locally generated clock.",
    "17. The method of claim 10, wherein said generating a clock output comprises: generating a phase from said rational numeric representation by integrating said rational numeric representation in conformity with periods of said stable clock source; and calculating representations of sinusoidal waveforms from said generated phase to generate a digital representation of said at least one substantially sinusoidal signal.",
    "18. The method of claim 10, wherein said generating a clock output comprises: dividing said clock output in conformity with a divisor input; comparing an output of said local divider with said stable clock with a phase/frequency detector; filtering a result of said comparing to generate a control signal; adjusting said divisor input in response to a delta-sigma modulation that receives said rational numeric representation; and generating said clock output with a voltage controlled oscillator from said result of said filtering.",
    "19. A circuit for providing a clock output synchronized to a timing reference signal supplied to a timing reference input, said circuit comprising: a numerically-controlled oscillator for providing said clock output and having an input for receiving a rational numeric representation of a ratio between a frequency of said clock output and a frequency of a stable clock for controlling said frequency of said clock output; a digital phase-frequency detector for generating a representation of an on-going phase-frequency difference between said timing reference signal and a signal derived from said clock output; a digital loop filter for filtering said representation of said on-going phase-frequency difference to provide said rational numeric representation to said numerically-controlled oscillator; a timing reference characteristic detection circuit for detecting a frequency range of said timing reference signal; and a ratio adjustment circuit for adjusting said rational numeric representation resulting from the filtering of the representation of the on-going phase-frequency difference in conformity with said detected frequency range.",
    "20. A circuit for providing a clock output synchronized to a timing reference signal supplied to a timing reference input, said circuit comprising: a numerically-controlled oscillator for providing said clock output and having an input for receiving a rational numeric representation of a ratio between a frequency of said clock output and a frequency of a stable clock for controlling said frequency of said clock output; a digital phase-frequency detector for generating a representation of an on-going phase-frequency difference between said timing reference signal and a signal derived from said clock output; a digital loop filter for filtering said representation of said on-going phase-frequency difference to provide said rational numeric representation to said numerically-controlled oscillator; a detection circuit for detecting absence of said timing reference signal at said timing reference input; and a selector for selecting an alternative source of timing reference in response to said detection circuit detecting said absence.",
    "21. The circuit of claim 20, wherein said selector selects between said timing reference input and a local reference clock signal for application to said phase-frequency detector.",
    "22. The circuit of claim 20, wherein said selector selects between an output of said digital loop filter and a fixed ratio representation to supply said rational numerical representation to said numerically controlled oscillator."
  ],
  "description_excerpt": "1. Field of the Invention\n\nThe present invention relates generally to phase-lock loop (PLL) clock generation circuits, and more specifically, to a numerically-controlled PLL for providing a clock signal synchronized to an input timing reference signal.\n\n2. Background of the Invention\n\nDigital audio systems are prevalent in the areas of home entertainment, professional production of multimedia and computer reproduction and generation of multimedia sources. Increasingly, digital audio data is transported from sub-system to sub-system and device to device in both consumer and professional installations, and the data is generally provided with, or has embedded, a timing reference that has too much jitter to act as a stable sample clock reference. Furthermore, the timing information may be provided at a frequency that is lower than the clock rate needed to operate a digital audio sink, such as a digital-to-analog converter (DAC) that receives the incoming digital audio data stream.\n\nTherefore, clock generation circuits that provide stable clock references synchronized to a digital audio stream's timing information are frequently required. The clock generating circuits must generally provide a low-jitter clock from a timing reference that may have a large amount of jitter present and/or from an additional interface clock that also may have a large amount of jitter. Further, such circuits in A/V applications must handle a wide range of potential input frequencies.",
  "cpc": [
    "H03L 7/148",
    "H03L 2207/50",
    "H03L 7/0994",
    "H03L 7/104",
    "H03L 7/113",
    "H03L 7/1976"
  ],
  "ipc": [
    "H03D 3/24"
  ],
  "assignees": [
    "Cirrus Logic Inc"
  ],
  "inventors": [
    "John L. Melanson",
    "Zhong You",
    "Scott Allan Woodford",
    "Steven Randall Green"
  ],
  "filing_date": "2007-03-22",
  "publication_date": "2010-06-29",
  "grant_date": "2010-06-29",
  "priority_date": "2007-03-22",
  "application_number": "US-68972907-A",
  "family_id": "42271243",
  "cited_by_count": 32,
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}