Storage device with an error correction unit and an improved arrangement for accessing and transferring blocks of data stored in a non-volatile semiconductor memory

{
  "publication_number": "US6317371B2",
  "country": "US",
  "kind": "B2",
  "title": "Storage device with an error correction unit and an improved arrangement for accessing and transferring blocks of data stored in a non-volatile semiconductor memory",
  "abstract": "In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.",
  "claims": [
    "1. A storage device comprising: a system interface unit carrying out interface with a host system via an external bus; a controller coupled with said system interface unit analyzing commands received by said system interface unit from said host system and controlling operations to be performed within said storage device; a non-volatile semiconductor memory coupled with said controller; an error correction unit, coupled with said non-volatile semiconductor memory, performing error detection and error correction for data stored in said non-volatile semiconductor memory; and two memories coupled between said system interface and said non-volatile semiconductor memory, wherein said non-volatile semiconductor memory is electrically erasable and electrically programmable and stores data from said host system via said system interface unit, wherein, in response to a read command, received by said system interface unit, for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, said controller carries out selective read operations of blocks of data to said two memories from said non-volatile semiconductor memory and carries out parallel operations of data transferring a first block of data, which has already been subjected to the error detection and error correction operation by said error correction unit, from one of said two memories to said host system via said system interface unit and of data transferring of a second block of data, to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of said two memories.",
    "2. A storage device comprising: a system interface unit carrying out interface with a host system via an external bus; a controller coupled with said system interface unit analyzing commands received by said system interface unit from said host system and controlling operations to be performed within said storage device; a non-volatile semiconductor memory coupled with said controller; an error correction unit, coupled with said non-volatile semiconductor memory, performing error detection and error correction for data stored in said non-volatile semiconductor memory; and two memories coupled between said system interface and said non-volatile semiconductor memory, wherein said non-volatile semiconductor memory is electrically erasable and electrically programmable and stores data from said host system via said system interface unit, wherein in response to a read command, received by said system interface unit, for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, said controller carries out selective read operations of blocks of data to said two memories from said non-volatile semiconductor memory and carries out a first operation of data transferring a first block of data which has already been subjected to the error detection and error correction operation by said error correction unit, from one of said two memories to said host system via said system interface unit while carrying out a second operation of data transferring of a second block of data to be subjected to the error detection and error correction operation from said non-volatile semiconductor memory to another of said two memories."
  ],
  "cpc": [
    "G11C 16/349",
    "G06F 12/16",
    "G11C 29/76",
    "G11C 29/88"
  ],
  "assignees": [
    "HITACHI LTD"
  ],
  "filing_date": "2001-04-04",
  "publication_date": "2001-11-13",
  "grant_date": "2001-11-13",
  "priority_date": "1996-02-29",
  "application_number": "US-82477801-A",
  "family_id": "12636443",
  "citations": [
    "JP3131951B2",
    "JPH03131951A",
    "JPH04308971A",
    "JPH04311236A",
    "JPH05274219A",
    "JPH0567005A",
    "JPH06124596A",
    "JPH0620483A",
    "JPH0756816A",
    "JPS62239252A",
    "JPS63219045A",
    "US5123016A",
    "US5844910A",
    "US6119245A"
  ]
}