Stacked semiconductor device and method of manufacturing the same

{
  "publication_number": "US9183890B2",
  "country": "US",
  "kind": "B2",
  "title": "Stacked semiconductor device and method of manufacturing the same",
  "abstract": "The stacked semiconductor device including a first chip, a second chip positioned on the first chip, the second chip being connected to a plurality of first penetration electrodes and including a first memory and a memory controller that are each controlled by the first chip, and a second memory positioned on the second chip and connected to a plurality of second penetration electrodes and controlled by the memory controller.",
  "claims": [
    "1. A stacked semiconductor device, comprising: a first chip including a cache-less microprocessor; a second chip positioned on the first chip, the second chip being connected to a plurality of first penetration electrodes, and the second chip including a first memory and a memory controller that are each to be controlled by the first chip; and a first layer including a second memory positioned on the second chip, the second memory being connected to a plurality of second penetration electrodes, and being controlled by the memory controller, wherein data stored in the first memory are accessed by the cache-less microprocessor directly, and data stored in the second memory are accessed by the cache-less microprocessor via the memory controller.",
    "2. The stacked semiconductor device as claimed in claim 1, wherein the first memory includes an L 1 cache, and the second memory includes an L 2 cache.",
    "3. The stacked semiconductor device as claimed in claim 2, wherein the cache-less microprocessor includes a plurality of cores, and wherein the first memory includes a plurality of L 1 core caches respectively connected to the plurality of cores and/or the plurality of first penetration electrodes via the first penetration electrodes.",
    "4. The stacked semiconductor device as claimed in claim 1, wherein the first memory includes a cache.",
    "5. The stacked semiconductor device as claimed in claim 1, wherein the second memory includes a system memory.",
    "6. The stacked semiconductor device as claimed in claim 1, further comprising a second layer including a third memory on the first layer including the second memory, the second layer including the third memory to be controlled by the memory controller via a plurality of third penetration electrodes.",
    "7. The stacked semiconductor device as claimed in claim 1, wherein the stacked semiconductor device is a smart phone or a solid state drive (SSD).",
    "8. A stacked semiconductor device comprising: a first chip; a second chip positioned on the first chip, the second chip being connected to a plurality of first penetration electrodes, and the second chip including a first memory and a memory controller that are each to be controlled by the first chip; a second memory positioned on the second chip, the second memory being connected to a plurality of second penetration electrodes, and being controlled by the memory controller; a third memory to be controlled by the memory controller via a plurality of third penetration electrodes, wherein: the third memory includes a flash memory and a solid state drive (SSD) controller to control the flash memory, and the memory controller is to control the SSD controller via the plurality of third penetration electrodes.",
    "9. A stacked semiconductor device, comprising: a stacked structure including a first chip, a second chip, a stack memory, and a plurality of penetration electrodes connecting corresponding overlapping portions of the first chip, the second chip and/or the stack memory to each other, wherein the second chip is stacked between the first chip and the stack memory in the stacked structure and wherein: the first chip includes a memory controller, the second chip includes a memory and a stack memory controller, the memory to be controlled by the memory controller of the first chip and the stack memory controller to control the stack memory via a corresponding one of the plurality of penetration electrodes, wherein the second chip is different from a core chip and wherein the stack memory excludes a memory controller.",
    "10. The stacked semiconductor device as claimed in claim 9, wherein a first group of the plurality of penetration electrodes extend across the second chip and a second group of the plurality of penetration electrodes extend across the stack memory.",
    "11. The stacked semiconductor device as claimed in claim 10, wherein the plurality of penetration electrodes connect to corresponding ones of a plurality of conductive microbumps respectively arranged between and electrically connected to corresponding portions of the first chip and/or corresponding ones of the plurality of first and second penetration electrodes.",
    "12. The stacked semiconductor device as claimed in claim 11, wherein conductive wires on a surface of the first chip are electrically connected to respective ones of the conductive microbumps arranged on corresponding portions of the surface of the first chip."
  ],
  "description_excerpt": "1. Field\n\nExample embodiments relate to integrated circuits (ICs), and more particularly, to a stacked semiconductor device that connects a central processing unit (CPU) to a memory via an electrical vertical element, and a method of manufacturing the same.\n\n2. Description of the Related Art\n\nPackaging of semiconductor ICs, e.g., memories, has been continuously developed in order to satisfy a demand for miniaturization and improve mounting efficiency. As more compact and high-performance electric/electronic products are in demand, various techniques for stacking memories are being developed.\n\nStacking of memories denotes a technique of vertically stacking at least two memories. The stacked memories may achieve a product with a memory capacity twice greater than that of a product achieved by a single-layer memory and may increase the efficiency of mounting area being used. Examples of a package in which a plurality of semiconductor chips are stacked include a stack-type semiconductor package in which a plurality of semiconductor chips or semiconductor device packages are stacked.\n\nOne or more embodiments provide a stacked semiconductor device including a relatively larger-sized cache and/or a relatively larger-sized system memory without increasing a chip area of a microprocessor, relative to conventional devices.",
  "cpc": [
    "G11C 5/02",
    "F16B 5/0275",
    "F21V 17/12",
    "F21V 23/026",
    "H01L 2224/0401",
    "H01L 2224/06181",
    "H01L 2224/13025",
    "H01L 2224/131",
    "H01L 2224/16146",
    "H01L 2224/16225",
    "H01L 2224/16227",
    "H01L 2224/17181",
    "H01L 2225/06513",
    "H01L 2225/06517",
    "H01L 2225/06541",
    "H01L 2225/06565",
    "H01L 25/0657",
    "H01L 25/18",
    "H01L 2924/014",
    "H01L 2924/15311",
    "H10W 72/07254",
    "H10W 72/244",
    "H10W 72/247",
    "H10W 72/252",
    "H10W 72/29",
    "H10W 72/944",
    "H10W 90/00",
    "H10W 90/26",
    "H10W 90/297",
    "H10W 90/722",
    "H10W 90/724"
  ],
  "ipc": [
    "G11C 5/02",
    "H01L 25/065",
    "H01L 25/18"
  ],
  "assignees": [
    "Samsung Electronics Co Ltd"
  ],
  "inventors": [
    "Jang Seok CHOI",
    "Ju-Yun JUNG"
  ],
  "filing_date": "2012-01-04",
  "publication_date": "2015-11-10",
  "grant_date": "2015-11-10",
  "priority_date": "2011-01-04",
  "application_number": "US-201213343072-A",
  "family_id": "46380653",
  "cited_by_count": 4,
  "citations": [
    "US20080126690A1",
    "US7518225B2",
    "US8554984B2",
    "US8008764B2",
    "KR20100094905A",
    "KR20100097454A",
    "US8274847B2"
  ]
}