Semiconductor memory device

{
  "publication_number": "US9504160B2",
  "country": "US",
  "kind": "B2",
  "title": "Semiconductor memory device",
  "abstract": "A semiconductor memory device is included. The semiconductor device includes a semiconductor memory device, comprising: a first substrate including a first semiconductor device mounted on the first substrate and a first connection terminal disposed at an edge of the first substrate; a second substrate including a second semiconductor device mounted on the second substrate and a second connection terminal at an edge of the second substrate; and an interface connector including a first socket portion configured to receive the first connection terminal and a second socket portion configured to receive the second connection terminal. The interface connector further includes: first socket terminals of the first socket portion are connected with the first connection terminals; second socket terminals of the second socket portion are connected with the second connection terminals; and an internal wiring for electrically connecting the first socket terminals with the second socket terminals.",
  "claims": [
    "1. A semiconductor memory device, comprising: a first substrate including a first semiconductor device mounted on the first substrate and a first connection terminal disposed at an edge of the first substrate; a second substrate including a second semiconductor device mounted on the second substrate and a second connection terminal disposed at an edge of the second substrate; an interface connector including a first socket portion configured to receive the first connection terminal and a second socket portion configured to receive the second connection terminal; and a case configured to receive the first substrate and the second substrate; wherein: the interface connector further includes: first socket terminals of the first socket portion are connected with the first connection terminals; second socket terminals of the second socket portion are connected with the second connection terminals; and an internal wiring for electrically connecting the first socket terminals with the second socket terminals; and at least a part of the interface connector is exposed outside of the case.",
    "2. The semiconductor memory device of claim 1, wherein the first socket portion and the second socket portion are disposed such that the first substrate and the second substrate are stacked in parallel with each other.",
    "3. The semiconductor memory device of claim 1, wherein at least one of the first substrate and the second substrate further comprises a main connector terminal at an edge other than an edge at which the first connection terminal or the second connection terminal is disposed.",
    "4. The semiconductor memory device of claim 1, wherein the interface connector is received in the case.",
    "5. The semiconductor memory device of claim 1, wherein a main connector terminal is provided on a surface of the interface connector exposed outside of the case.",
    "6. The semiconductor memory device of claim 5, wherein a part of the interface connector on which the main connector terminal is provided has a connector dimension according to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Small Computer System Interface (SCSI) standard, the Peripheral Component Interconnect (PCI) interface standard, or the Serial Attached SCSI (SAS) standard.",
    "7. The semiconductor memory device of claim 1, further comprising: at least two main connector terminals coupled to at least one of the first substrate and the second substrate; wherein at least one of the at least two main connector terminals is formed according to a different standard or a different form factors that another of the at least two main connector terminals.",
    "8. The semiconductor memory device of claim 1, further comprising: an electronic element in the interface connector; wherein the electronic element is electrically connected with at least one of the first socket terminal and the second socket terminal.",
    "9. The semiconductor memory device of claim 1, wherein the interface connector is formed integrally with the case.",
    "10. The semiconductor memory device of claim 9, further comprising a main connector terminal disposed on a surface of the case.",
    "11. The semiconductor memory device of claim 1, further comprising: a main connector terminal disposed on a surface of the interface connector; wherein the first substrate and the second substrate are fixed to each other by an adhesive member.",
    "12. A semiconductor memory device comprising: a first substrate including a first semiconductor device mounted on the first substrate and a first connection terminal disposed at an edge of the first substrate; a second substrate including a second semiconductor device mounted on the second substrate and a second connection terminal disposed at an edge of the second substrate; an interface connector comprising a first socket portion configured to receive the first connection terminal and a second socket portion configured to receive the second connection terminal; and a case exposing the interface connector and configured to receive the first substrate and the second substrate; wherein a main connector terminal is disposed on a surface of the interface connector.",
    "13. A semiconductor memory device, comprising: an interface connector comprising a plurality of socket portions disposed on a side of the interface connector; a plurality of substrates, each substrate including a semiconductor device and including a connection terminal contacting a corresponding socket portion of the interface connector; a case substantially surrounding the substrates and including an opening; and a main connector terminal disposed on one of the substrates; and an adhesive member coupled between the substrates; wherein a semiconductor device of the substrates without the main connector terminal are configured to be accessed through the main connector terminal and the interface connector.",
    "14. The semiconductor memory device of claim 13, wherein the case substantially surrounds the interface connector.",
    "15. The semiconductor memory device of claim 13, wherein: the main connector terminal comprises a plurality of main connector terminals; and each main connector terminal is configured to present a standard interface and provide access to the semiconductor devices of the substrates.",
    "16. The semiconductor memory device of claim 13, wherein at least one of the substrates includes a memory controller."
  ],
  "description_excerpt": "Embodiments relate to a semiconductor memory device, and more particularly, to a semiconductor memory device that is favorable to miniaturization, is easy to manufacture, and is partially replaceable.\n\nFor electronic devices, small sizes and high capacities have been demanded at the same time. Although the number of semiconductor devices mounted on a substrate having a limited area needs to be increased for high capacities, the area of the substrate needs to be reduced for small sizes. To meet the conflicting needs, a scheme has been proposed in which semiconductor devices to be mounted on one large substrate are mounted on two smaller substrates. To electrically connect the two smaller substrates, connectors are provided corresponding to positions of the substrates, respectively, for interconnection or a flexible printed circuit board is used. However, these methods are not useful because the semiconductor devices are mountable on only facing surfaces or utilization of the area is not efficient.\n\nAn embodiment includes a semiconductor device including a semiconductor memory device, comprising: a first substrate including a first semiconductor device mounted on the first substrate and a first connection terminal disposed at an edge of the first substrate; a second substrate including a second semiconductor device mounted on the second substrate and a second connection terminal at an edge of the second substrate; and an interface connector including a first socket portion configured to receive the first connection terminal and a second socket portion configured to receive the second connection terminal.",
  "cpc": [
    "H05K 1/181",
    "G06F 13/00",
    "H01R 12/7082",
    "H01R 12/721",
    "H05K 1/117",
    "H05K 2201/10159",
    "Y02P 70/50",
    "Y02P 70/611"
  ],
  "ipc": [
    "H05K 1/18",
    "H01R 12/70",
    "H05K 5/00"
  ],
  "assignees": [
    "Samsung Electronics Co Ltd"
  ],
  "inventors": [
    "Teck-su OH",
    "Sung-Ki Lee"
  ],
  "filing_date": "2014-11-19",
  "publication_date": "2016-11-22",
  "grant_date": "2016-11-22",
  "priority_date": "2013-11-20",
  "application_number": "US-201414548261-A",
  "family_id": "53173090",
  "cited_by_count": 2,
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}