Patent · US10884195B2 · B2 · US
Techniques to support multiple interconnect protocols for a common set of interconnect connectors
- (11) Publication number
- US10884195B2
- (21) Application number
- 15/396,501
- (22) Filing date
- 2016-12-31
- (30) Priority date
- 2016-07-22
- (43) Publication date
- 2021-01-05
- (45) Date of grant
- 2021-01-05
- (51) IPC
- B25J 15/00; B65G 1/04; G02B 6/38; G02B 6/42; G02B 6/44; G05D 23/19; G05D 23/20; G06F 1/18; G06F 1/20; G06F 11/14; G06F 11/34; G06F 12/0862; G06F 12/0893; G06F 12/10; G06F 12/109; G06F 12/14; G06F 13/16; G06F 13/40; G06F 13/42; G06F 15/80; G06F 16/901; G06F 3/06; G06F 8/65; G06F 9/30; G06F 9/38; G06F 9/4401; G06F 9/50; G06F 9/54; G06Q 10/00; G06Q 10/06; G06Q 10/08; G06Q 50/04; G07C 5/00; G08C 17/02; G11C 11/56; G11C 14/00; G11C 5/02; G11C 5/06; G11C 7/10; H03M 7/30; H03M 7/40; H04B 10/25; H04L 12/24; H04L 12/26; H04L 12/28; H04L 12/751; H04L 12/781; H04L 12/811; H04L 12/851; H04L 12/911; H04L 12/919; H04L 12/927; H04L 12/931; H04L 12/933; H04L 12/939; H04L 12/947; H04L 29/06; H04L 29/08; H04L 29/12; H04L 9/06; H04L 9/14; H04L 9/32; H04Q 1/04; H04Q 11/00; H04W 4/02; H04W 4/80; H05K 1/02; H05K 1/18; H05K 13/04; H05K 5/02; H05K 7/14; H05K 7/20
- (52) CPC
- G06F Electric digital data processing: 3/061, 1/183, 1/20, 11/141, 11/3414, 12/0862, 12/0893, 12/10, 12/109, 12/1408, 13/161, 13/1668, 13/1694, 13/385, 13/4022, 13/4068, 13/409, 13/42, 13/4282, 15/161, 15/8061, 16/1748, 16/9014, 2209/483, 2209/5019, 2209/5022, 2212/1008, 2212/1024, 2212/1041, 2212/1044, 2212/152, 2212/202, 2212/401, 2212/402, 2212/7207, 3/0611, 3/0613, 3/0616, 3/0619, 3/0625, 3/0631, 3/0638, 3/064, 3/0647, 3/065, 3/0653, 3/0655, 3/0658, 3/0659, 3/0664, 3/0665, 3/067, 3/0673, 3/0679, 3/0683, 3/0688, 3/0689, 8/65, 9/30036, 9/3887, 9/4401, 9/4881, 9/5016, 9/5027, 9/5044, 9/505, 9/5072, 9/5077, 9/544
- B25J Manipulators; chambers provided with manipulation devices: 15/0014
- B65G Transport or storage devices, e.g. conveyors for loading or tipping, shop conveyor systems or pneumatic tube conveyors: 1/0492
- G02B Optical elements, systems or apparatus: 6/3882, 6/3893, 6/3897, 6/4292, 6/4452
- G05D Systems for controlling or regulating non-electric variables: 23/1921, 23/2039
- G06Q Information and communication technology [ICT] specially adapted for administrative, commercial, financial, managerial or supervisory purposes; systems or methods specially adapted for administrative, commercial, financial, managerial or supervisory purposes, not otherwise provided for: 10/06, 10/06314, 10/087, 10/20, 50/04
- G07C Time or attendance registers; registering or indicating the working of machines; generating random numbers; voting or lottery apparatus; arrangements, systems or apparatus for checking not provided for elsewhere: 5/008
- G08C Transmission systems for measured values, control or similar signals: 17/02, 2200/00
- G11C Static stores: 11/56, 14/0009, 5/02, 5/06, 7/1072
- H03M Coding; decoding; code conversion in general: 7/30, 7/3084, 7/3086, 7/40, 7/4031, 7/4056, 7/4081, 7/6005, 7/6023
- H04B Transmission: 10/25, 10/25891
- H04J Multiplex communication: 14/00
- H04L Transmission of digital information, e.g. telegraphic communication: 12/2809, 29/12009, 41/024, 41/046, 41/0813, 41/082, 41/0896, 41/12, 41/145, 41/147, 41/149, 41/40, 41/5019, 43/065, 43/08, 43/0817, 43/0876, 43/0894, 43/16, 45/02, 45/52, 47/24, 47/38, 47/765, 47/782, 47/805, 47/82, 47/823, 47/83, 49/00, 49/15, 49/25, 49/35, 49/357, 49/45, 49/555, 61/00, 67/02, 67/10, 67/1004, 67/1008, 67/1012, 67/1014, 67/1029, 67/1034, 67/1097, 67/12, 67/16, 67/306, 67/34, 67/51, 69/04, 69/18, 69/329, 9/0643, 9/14, 9/3247, 9/3263
- H04Q Selecting: 1/04, 1/09, 11/00, 11/0003, 11/0005, 11/0062, 11/0071, 2011/0037, 2011/0041, 2011/0052, 2011/0073, 2011/0079, 2011/0086, 2213/13523, 2213/13527
- H04W Wireless communication networks: 4/023, 4/80
- H05K Printed circuits; casings or constructional details of electric apparatus; manufacture of assemblages of electrical components: 1/0203, 1/181, 13/0486, 2201/066, 2201/10121, 2201/10159, 2201/10189, 5/0204, 7/1418, 7/1421, 7/1422, 7/1442, 7/1447, 7/1461, 7/1485, 7/1487, 7/1489, 7/1491, 7/1492, 7/1498, 7/2039, 7/20709, 7/20727, 7/20736, 7/20745, 7/20836
- Y02D Climate change mitigation technologies in information and communication technologies [ICT], i.e. information and communication technologies aiming at the reduction of their own energy use: 10/00
- Y02P Climate change mitigation technologies in the production or processing of goods: 90/30
- Y04S Systems integrating technologies related to power network operation, communication or information technologies for improving the electrical power generation, transmission, distribution, management or usage, i.e. smart grids: 10/50, 10/52
- Y10S Technical subjects covered by former uspc cross-reference art collections [xracs] and digests: 901/01, 901/30
- (73) Assignee
- Intel Corp
- (72) Inventors
- Mahesh Wagh; Mark S. Myers; Stephen R. Van Doren; Dimitrios Ziakas; Bassam Coury
- (54) Title
- Techniques to support multiple interconnect protocols for a common set of interconnect connectors
- (57) Abstract
Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.
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Claims (25)
- An apparatus, comprising: a physical (PHY) layer interface comprising a plurality of connectors configured to couple with one or more other devices, and to send and receive data via the plurality of connectors; interface logic coupled with the PHY layer interface, the interface logic to cause processing of the data for communication via a first subset of the plurality of connectors in accordance with a first interconnect protocol and to cause processing of the data for communication via a second subset of the plurality of connectors in accordance with a second interconnect protocol, the first interconnect protocol and the second interconnect protocol are different protocols, where the first interconnect protocol is a serial link protocol, and the second interconnect protocol is a coherent link protocol or an accelerator link protocol; and the interface logic to cause processing of the data for communication in accordance with the first interconnect protocol and the second interconnect protocol with active protocol agents associated with the first interconnect protocol and the second interconnect protocol and one or more protocol maps and routing tables configured based on the active protocol agents.
- The apparatus of claim 1, the interface logic to cause processing of the data for communication via a third subset of the plurality of connectors in accordance with a third interconnect protocol, the third interconnect protocol different than the first interconnect protocol and the second interconnect protocol and the third interconnect protocol is selected from the coherent link protocol or the accelerator link protocol.
- The apparatus of claim 1, comprising: fuse logic; and one or more fuses coupled with the interface logic, the one or more fuses programmable to associate the first interconnect protocol with the first subset of the plurality of connectors and to associate the second interconnect protocol with the second subset of the plurality of connectors.
- The apparatus of claim 3, wherein the one or more fuses are statically programmable to prevent changes to which interconnect protocols are associated with particular subsets of the plurality of connectors.
- The apparatus of claim 3, wherein the one or more fuses are reprogrammable to associate a third interconnect protocol with at least one of the first subset of the plurality of connectors and the second subset of the plurality of connectors, the third interconnect protocol different than at least one of the first interconnect protocol and the second interconnect protocol.
- The apparatus of claim 1, wherein the interface logic to cause processing of the data for communication via the plurality of connectors in accordance with the first interconnect protocol and the second interconnect protocol based on a setting in a Basic Input/Output System (BIOS).
- The apparatus of claim 6, comprising: the BIOS; and one or more fuses coupled with the BIOS, the one or more fuses programmable to associate the first interconnect protocol with the first subset of the plurality of connectors and the second interconnect protocol with the second subset of the plurality of connectors.
- The apparatus of claim 1, wherein the interface logic to associate the first interconnect protocol with the first subset of the plurality of connectors and the second interconnect protocol with the second subset of the plurality of connectors based on a signal generated based on a first device coupled with the first subset and a second device coupled with the second subset.
- The apparatus of claim 1, the interface logic to dynamically change at least one of an association of the first interconnect protocol with the first subset of the plurality of connectors and the second interconnect protocol with the second subset of the plurality of connectors to a different interconnect protocol based on a signal generated by an application during run-time.
- A non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed, enable processing circuitry to: determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols, where the first interconnect protocol is a serial link protocol, and the second interconnect protocol is a coherent link protocol or an accelerator link protocol; activate protocol agents for the first interconnect protocol and the second interconnect protocol; configure one or more protocol maps and routing tables based on the active protocol agents; cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol with the one or more protocol maps and routing tables; and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol with the one or more protocol maps and routing tables.
- The non-transitory computer-readable storage medium of claim 10, comprising a plurality of instructions, that when executed, enable processing circuitry to: associate a third interconnect protocol with a third subset of the plurality of connectors based on the configuration, the third interconnect protocol different than the first interconnect protocol and the second interconnect protocol and the third interconnect protocol is the coherent link protocol or the accelerator link protocol; and cause processing of data for communication via the third subset of the plurality of connectors in accordance with the third interconnect protocol.
- The non-transitory computer-readable storage medium of claim 10, comprising a plurality of instructions, that when executed, enable processing circuitry to detect one or more fuses to determine the configuration to associate the first interconnect protocol with the first subset of the plurality of connectors and to associate the second interconnect protocol with the second subset of the plurality of connectors.
- The non-transitory computer-readable storage medium of claim 12, wherein the one or more fuses are statically programmable to prevent changes to which interconnect protocols are associated with particular subsets of the plurality of connectors.
- The non-transitory computer-readable storage medium of claim 12, wherein the one or more fuses are reprogrammable to associate a different interconnect protocol with at least one of the first subset of the plurality of connectors and the second subset of the plurality of connectors, the different interconnect protocol different than at least one of the first interconnect protocol and the second interconnect protocol.
- The non-transitory computer-readable storage medium of claim 10, comprising a plurality of instructions, that when executed, enable processing circuitry to determine the configuration based on a setting in a Basic Input/Output System (BIOS) or in a read-only memory.
- The non-transitory computer-readable storage medium of claim 10, comprising a plurality of instructions, that when executed, enable processing circuitry to associate the first interconnect protocol with the first subset of the plurality of connectors and the second interconnect protocol with the second subset of the plurality of connectors based on a signal generated from a first device coupling with the first subset and a second device coupling with the second subset.
- The non-transitory computer-readable storage medium of claim 10, comprising a plurality of instructions, that when executed, enable processing circuitry to dynamically change at least one of an association of the first interconnect protocol with the first subset of the plurality of connectors and the second interconnect protocol with the second subset of the plurality of connectors to a different interconnect protocol based on a signal generated by an application during run-time.
- A computer-implemented method, comprising: determining a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols, where the first interconnect protocol is a serial link protocol, and the second interconnect protocol is a coherent link protocol or an accelerator link protocol; activating protocol agents for the first interconnect protocol and the second interconnect protocol; configuring one or more protocol maps and routing tables based on the active protocol agents; causing processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol with the one or more protocol maps and routing tables; and causing processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol with the one or more protocol maps and routing tables.
- The computer-implemented method of claim 18, comprising: associating a third interconnect protocol with a third subset of the plurality of connectors based on the configuration, the third interconnect protocol different than the first interconnect protocol and the second interconnect protocol and the third interconnect protocol is the coherent link protocol or the accelerator link protocol; and causing processing of data for communication via the third subset of the plurality of connectors in accordance with the third interconnect protocol.
- The computer-implemented method of claim 18, comprising: detecting one or more fuses to determine the configuration to associate the first interconnect protocol with the first subset of the plurality of connectors and to associate the second interconnect protocol with the second subset of the plurality of connectors.
- The computer-implemented method of claim 20, wherein the one or more fuses are statically programmable to prevent changes to which interconnect protocols are associated with particular subsets of the plurality of connectors.
- The computer-implemented method of claim 20, wherein the one or more fuses are reprogrammable to associate a different interconnect protocol with at least one of the first subset of the plurality of connectors and the second subset of the plurality of connectors, the different interconnect protocol different than at least one of the first interconnect protocol and the second interconnect protocol.
- The computer-implemented method of claim 18, comprising: determining the configuration based on a setting in a Basic Input/Output System (BIOS) or in a read-only memory.
- The computer-implemented method of claim 18, comprising: associating the first interconnect protocol with the first subset of the plurality of connectors and the second interconnect protocol with the second subset of the plurality of connectors based on a signal generated from a first device coupling with the first subset and a second device coupling with the second subset.
- The computer-implemented method of claim 18, comprising: dynamically changing at least one of an association of the first interconnect protocol with the first subset of the plurality of connectors and the second interconnect protocol with the second subset of the plurality of connectors to a different interconnect protocol based on a signal generated by an application during run-time.
Description
This application claims priority to U.S. Provisional Patent Application No. 62/365,969, filed Jul. 22, 2016, U.S. Provisional Patent Application No. 62/376,859, filed Aug. 18, 2016, and U.S. Provisional Patent Application No. 62/427,268, filed Nov. 29, 2016, each of which are hereby incorporated by reference in their entirety.
Embodiments described herein generally include techniques to support multiple interconnect protocols for a common set of interconnect connectors.
As computing systems are advancing, the components therein are becoming more complex. As a result, the interconnect architecture to couple and communicate between the components is also increasing in complexity to ensure bandwidth and latency requirements are met for optimal component operation. Furthermore, different market segments need different interconnect architectures to suit the market's needs and different interconnect connections. For example, these computing systems may provide various processing capabilities that require different add-in cards having physical resources. These add-in cards that may be coupled with the baseboard and may require any number of different interconnect protocols. However, connector space on the baseboard may be limited and a single connector typical supports on a single or limited number of interconnect protocols. Thus, embodiments may be directed to solving these and other problems.
Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.
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Record as JSON
{
"publication_number": "US10884195B2",
"country": "US",
"kind": "B2",
"title": "Techniques to support multiple interconnect protocols for a common set of interconnect connectors",
"abstract": "Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.",
"claims": [
"1. An apparatus, comprising: a physical (PHY) layer interface comprising a plurality of connectors configured to couple with one or more other devices, and to send and receive data via the plurality of connectors; interface logic coupled with the PHY layer interface, the interface logic to cause processing of the data for communication via a first subset of the plurality of connectors in accordance with a first interconnect protocol and to cause processing of the data for communication via a second subset of the plurality of connectors in accordance with a second interconnect protocol, the first interconnect protocol and the second interconnect protocol are different protocols, where the first interconnect protocol is a serial link protocol, and the second interconnect protocol is a coherent link protocol or an accelerator link protocol; and the interface logic to cause processing of the data for communication in accordance with the first interconnect protocol and the second interconnect protocol with active protocol agents associated with the first interconnect protocol and the second interconnect protocol and one or more protocol maps and routing tables configured based on the active protocol agents.",
"2. The apparatus of claim 1, the interface logic to cause processing of the data for communication via a third subset of the plurality of connectors in accordance with a third interconnect protocol, the third interconnect protocol different than the first interconnect protocol and the second interconnect protocol and the third interconnect protocol is selected from the coherent link protocol or the accelerator link protocol.",
"3. The apparatus of claim 1, comprising: fuse logic; and one or more fuses coupled with the interface logic, the one or more fuses programmable to associate the first interconnect protocol with the first subset of the plurality of connectors and to associate the second interconnect protocol with the second subset of the plurality of connectors.",
"4. The apparatus of claim 3, wherein the one or more fuses are statically programmable to prevent changes to which interconnect protocols are associated with particular subsets of the plurality of connectors.",
"5. The apparatus of claim 3, wherein the one or more fuses are reprogrammable to associate a third interconnect protocol with at least one of the first subset of the plurality of connectors and the second subset of the plurality of connectors, the third interconnect protocol different than at least one of the first interconnect protocol and the second interconnect protocol.",
"6. The apparatus of claim 1, wherein the interface logic to cause processing of the data for communication via the plurality of connectors in accordance with the first interconnect protocol and the second interconnect protocol based on a setting in a Basic Input/Output System (BIOS).",
"7. The apparatus of claim 6, comprising: the BIOS; and one or more fuses coupled with the BIOS, the one or more fuses programmable to associate the first interconnect protocol with the first subset of the plurality of connectors and the second interconnect protocol with the second subset of the plurality of connectors.",
"8. The apparatus of claim 1, wherein the interface logic to associate the first interconnect protocol with the first subset of the plurality of connectors and the second interconnect protocol with the second subset of the plurality of connectors based on a signal generated based on a first device coupled with the first subset and a second device coupled with the second subset.",
"9. The apparatus of claim 1, the interface logic to dynamically change at least one of an association of the first interconnect protocol with the first subset of the plurality of connectors and the second interconnect protocol with the second subset of the plurality of connectors to a different interconnect protocol based on a signal generated by an application during run-time.",
"10. A non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed, enable processing circuitry to: determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols, where the first interconnect protocol is a serial link protocol, and the second interconnect protocol is a coherent link protocol or an accelerator link protocol; activate protocol agents for the first interconnect protocol and the second interconnect protocol; configure one or more protocol maps and routing tables based on the active protocol agents; cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol with the one or more protocol maps and routing tables; and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol with the one or more protocol maps and routing tables.",
"11. The non-transitory computer-readable storage medium of claim 10, comprising a plurality of instructions, that when executed, enable processing circuitry to: associate a third interconnect protocol with a third subset of the plurality of connectors based on the configuration, the third interconnect protocol different than the first interconnect protocol and the second interconnect protocol and the third interconnect protocol is the coherent link protocol or the accelerator link protocol; and cause processing of data for communication via the third subset of the plurality of connectors in accordance with the third interconnect protocol.",
"12. The non-transitory computer-readable storage medium of claim 10, comprising a plurality of instructions, that when executed, enable processing circuitry to detect one or more fuses to determine the configuration to associate the first interconnect protocol with the first subset of the plurality of connectors and to associate the second interconnect protocol with the second subset of the plurality of connectors.",
"13. The non-transitory computer-readable storage medium of claim 12, wherein the one or more fuses are statically programmable to prevent changes to which interconnect protocols are associated with particular subsets of the plurality of connectors.",
"14. The non-transitory computer-readable storage medium of claim 12, wherein the one or more fuses are reprogrammable to associate a different interconnect protocol with at least one of the first subset of the plurality of connectors and the second subset of the plurality of connectors, the different interconnect protocol different than at least one of the first interconnect protocol and the second interconnect protocol.",
"15. The non-transitory computer-readable storage medium of claim 10, comprising a plurality of instructions, that when executed, enable processing circuitry to determine the configuration based on a setting in a Basic Input/Output System (BIOS) or in a read-only memory.",
"16. The non-transitory computer-readable storage medium of claim 10, comprising a plurality of instructions, that when executed, enable processing circuitry to associate the first interconnect protocol with the first subset of the plurality of connectors and the second interconnect protocol with the second subset of the plurality of connectors based on a signal generated from a first device coupling with the first subset and a second device coupling with the second subset.",
"17. The non-transitory computer-readable storage medium of claim 10, comprising a plurality of instructions, that when executed, enable processing circuitry to dynamically change at least one of an association of the first interconnect protocol with the first subset of the plurality of connectors and the second interconnect protocol with the second subset of the plurality of connectors to a different interconnect protocol based on a signal generated by an application during run-time.",
"18. A computer-implemented method, comprising: determining a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols, where the first interconnect protocol is a serial link protocol, and the second interconnect protocol is a coherent link protocol or an accelerator link protocol; activating protocol agents for the first interconnect protocol and the second interconnect protocol; configuring one or more protocol maps and routing tables based on the active protocol agents; causing processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol with the one or more protocol maps and routing tables; and causing processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol with the one or more protocol maps and routing tables.",
"19. The computer-implemented method of claim 18, comprising: associating a third interconnect protocol with a third subset of the plurality of connectors based on the configuration, the third interconnect protocol different than the first interconnect protocol and the second interconnect protocol and the third interconnect protocol is the coherent link protocol or the accelerator link protocol; and causing processing of data for communication via the third subset of the plurality of connectors in accordance with the third interconnect protocol.",
"20. The computer-implemented method of claim 18, comprising: detecting one or more fuses to determine the configuration to associate the first interconnect protocol with the first subset of the plurality of connectors and to associate the second interconnect protocol with the second subset of the plurality of connectors.",
"21. The computer-implemented method of claim 20, wherein the one or more fuses are statically programmable to prevent changes to which interconnect protocols are associated with particular subsets of the plurality of connectors.",
"22. The computer-implemented method of claim 20, wherein the one or more fuses are reprogrammable to associate a different interconnect protocol with at least one of the first subset of the plurality of connectors and the second subset of the plurality of connectors, the different interconnect protocol different than at least one of the first interconnect protocol and the second interconnect protocol.",
"23. The computer-implemented method of claim 18, comprising: determining the configuration based on a setting in a Basic Input/Output System (BIOS) or in a read-only memory.",
"24. The computer-implemented method of claim 18, comprising: associating the first interconnect protocol with the first subset of the plurality of connectors and the second interconnect protocol with the second subset of the plurality of connectors based on a signal generated from a first device coupling with the first subset and a second device coupling with the second subset.",
"25. The computer-implemented method of claim 18, comprising: dynamically changing at least one of an association of the first interconnect protocol with the first subset of the plurality of connectors and the second interconnect protocol with the second subset of the plurality of connectors to a different interconnect protocol based on a signal generated by an application during run-time."
],
"description_excerpt": "This application claims priority to U.S. Provisional Patent Application No. 62/365,969, filed Jul. 22, 2016, U.S. Provisional Patent Application No. 62/376,859, filed Aug. 18, 2016, and U.S. Provisional Patent Application No. 62/427,268, filed Nov. 29, 2016, each of which are hereby incorporated by reference in their entirety.\n\nEmbodiments described herein generally include techniques to support multiple interconnect protocols for a common set of interconnect connectors.\n\nAs computing systems are advancing, the components therein are becoming more complex. As a result, the interconnect architecture to couple and communicate between the components is also increasing in complexity to ensure bandwidth and latency requirements are met for optimal component operation. Furthermore, different market segments need different interconnect architectures to suit the market's needs and different interconnect connections. For example, these computing systems may provide various processing capabilities that require different add-in cards having physical resources. These add-in cards that may be coupled with the baseboard and may require any number of different interconnect protocols. However, connector space on the baseboard may be limited and a single connector typical supports on a single or limited number of interconnect protocols. Thus, embodiments may be directed to solving these and other problems.\n\nEmbodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.",
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],
"assignees": [
"Intel Corp"
],
"inventors": [
"Mahesh Wagh",
"Mark S. Myers",
"Stephen R. Van Doren",
"Dimitrios Ziakas",
"Bassam Coury"
],
"filing_date": "2016-12-31",
"publication_date": "2021-01-05",
"grant_date": "2021-01-05",
"priority_date": "2016-07-22",
"application_number": "US-201615396501-A",
"family_id": "60804962",
"cited_by_count": 0,
"citations": [
"US6201404B1",
"US20030072271A1",
"US20030182495A1",
"US20120203937A1",
"US20110183546A1",
"US20110206063A1",
"US20130297845A1",
"US20140019653A1",
"US20140181352A1",
"US20150134868A1",
"US20160156137A1",
"US20160259005A1",
"US20160335221A1"
]
}
Record 1,817 of 8,000 in Patents full text (MLC-0201). Request the full dataset.