Patent · US11184261B2 · B2 · US
Techniques to configure physical compute resources for workloads via circuit switching
- (11) Publication number
- US11184261B2
- (21) Application number
- 15/396,473
- (22) Filing date
- 2016-12-31
- (30) Priority date
- 2016-07-22
- (43) Publication date
- 2021-11-23
- (45) Date of grant
- 2021-11-23
- (51) IPC
- B25J 15/00; B65G 1/04; G02B 6/38; G02B 6/42; G02B 6/44; G05D 23/19; G05D 23/20; G06F 1/18; G06F 1/20; G06F 11/14; G06F 11/34; G06F 12/0862; G06F 12/0893; G06F 12/10; G06F 12/109; G06F 12/14; G06F 13/16; G06F 13/40; G06F 13/42; G06F 15/16; G06F 15/80; G06F 16/901; G06F 3/06; G06F 8/65; G06F 9/30; G06F 9/38; G06F 9/4401; G06F 9/50; G06F 9/54; G06Q 10/00; G06Q 10/06; G06Q 10/08; G06Q 50/04; G07C 5/00; G08C 17/02; G11C 11/56; G11C 14/00; G11C 5/02; G11C 5/06; G11C 7/10; H03M 7/30; H03M 7/40; H04B 10/25; H04J 14/00; H04L 12/24; H04L 12/26; H04L 12/28; H04L 12/751; H04L 12/781; H04L 12/811; H04L 12/851; H04L 12/911; H04L 12/919; H04L 12/927; H04L 12/931; H04L 12/933; H04L 12/939; H04L 12/947; H04L 29/06; H04L 29/08; H04L 29/12; H04L 9/06; H04L 9/14; H04L 9/32; H04Q 1/04; H04Q 11/00; H04W 4/02; H04W 4/80; H05K 1/02; H05K 1/18; H05K 13/04; H05K 5/02; H05K 7/14; H05K 7/20
- (52) CPC
- G06F Electric digital data processing: 3/061, 1/183, 1/20, 11/141, 11/3414, 12/0862, 12/0893, 12/10, 12/109, 12/1408, 13/161, 13/1668, 13/1694, 13/385, 13/4022, 13/4068, 13/409, 13/42, 13/4282, 15/161, 15/8061, 16/1748, 16/9014, 2209/483, 2209/5019, 2209/5022, 2212/1008, 2212/1024, 2212/1041, 2212/1044, 2212/152, 2212/202, 2212/401, 2212/402, 2212/7207, 3/0611, 3/0613, 3/0616, 3/0619, 3/0625, 3/0631, 3/0638, 3/064, 3/0647, 3/065, 3/0653, 3/0655, 3/0658, 3/0659, 3/0664, 3/0665, 3/067, 3/0673, 3/0679, 3/0683, 3/0688, 3/0689, 8/65, 9/30036, 9/3887, 9/4401, 9/4881, 9/5016, 9/5027, 9/5044, 9/505, 9/5072, 9/5077, 9/544
- B25J Manipulators; chambers provided with manipulation devices: 15/0014
- B65G Transport or storage devices, e.g. conveyors for loading or tipping, shop conveyor systems or pneumatic tube conveyors: 1/0492
- G02B Optical elements, systems or apparatus: 6/3882, 6/3893, 6/3897, 6/4292, 6/4452
- G05D Systems for controlling or regulating non-electric variables: 23/1921, 23/2039
- G06Q Information and communication technology [ICT] specially adapted for administrative, commercial, financial, managerial or supervisory purposes; systems or methods specially adapted for administrative, commercial, financial, managerial or supervisory purposes, not otherwise provided for: 10/06, 10/06314, 10/087, 10/20, 50/04
- G07C Time or attendance registers; registering or indicating the working of machines; generating random numbers; voting or lottery apparatus; arrangements, systems or apparatus for checking not provided for elsewhere: 5/008
- G08C Transmission systems for measured values, control or similar signals: 17/02, 2200/00
- G11C Static stores: 11/56, 14/0009, 5/02, 5/06, 7/1072
- H03M Coding; decoding; code conversion in general: 7/30, 7/3084, 7/3086, 7/40, 7/4031, 7/4056, 7/4081, 7/6005, 7/6023
- H04B Transmission: 10/25, 10/25891
- H04J Multiplex communication: 14/00
- H04L Transmission of digital information, e.g. telegraphic communication: 12/2809, 29/12009, 41/024, 41/046, 41/0813, 41/082, 41/0896, 41/12, 41/145, 41/147, 41/149, 41/40, 41/5019, 43/065, 43/08, 43/0817, 43/0876, 43/0894, 43/16, 45/02, 45/52, 47/24, 47/38, 47/765, 47/782, 47/805, 47/82, 47/823, 47/83, 49/00, 49/15, 49/25, 49/35, 49/357, 49/45, 49/555, 61/00, 67/02, 67/10, 67/1004, 67/1008, 67/1012, 67/1014, 67/1029, 67/1034, 67/1097, 67/12, 67/16, 67/306, 67/34, 67/51, 69/04, 69/18, 69/329, 9/0643, 9/14, 9/3247, 9/3263
- H04Q Selecting: 1/04, 1/09, 11/00, 11/0003, 11/0005, 11/0062, 11/0071, 2011/0037, 2011/0041, 2011/0052, 2011/0073, 2011/0079, 2011/0086, 2213/13523, 2213/13527
- H04W Wireless communication networks: 4/023, 4/80
- H05K Printed circuits; casings or constructional details of electric apparatus; manufacture of assemblages of electrical components: 1/0203, 1/181, 13/0486, 2201/066, 2201/10121, 2201/10159, 2201/10189, 5/0204, 7/1418, 7/1421, 7/1422, 7/1442, 7/1447, 7/1461, 7/1485, 7/1487, 7/1489, 7/1491, 7/1492, 7/1498, 7/2039, 7/20709, 7/20727, 7/20736, 7/20745, 7/20836
- Y02D Climate change mitigation technologies in information and communication technologies [ICT], i.e. information and communication technologies aiming at the reduction of their own energy use: 10/00
- Y02P Climate change mitigation technologies in the production or processing of goods: 90/30
- Y04S Systems integrating technologies related to power network operation, communication or information technologies for improving the electrical power generation, transmission, distribution, management or usage, i.e. smart grids: 10/50, 10/52
- Y10S Technical subjects covered by former uspc cross-reference art collections [xracs] and digests: 901/01, 901/30
- (73) Assignee
- INTEL CORP
- (72) Inventors
- NACHIMUTHU MURUGASAMY K; KUMAR MOHAN J
- (54) Title
- Techniques to configure physical compute resources for workloads via circuit switching
- (57) Abstract
Embodiments are generally directed apparatuses, methods, techniques and so forth to select two or more processing units of the plurality of processing units to process a workload, and configure a circuit switch to link the two or more processing units to process the workload, the two or more processing units each linked to each other via paths of communication and the circuit switch.
- Full text
- View on Google Patents
Claims (25)
- An apparatus, comprising: a circuit switch; and a switching controller to: link two or more accelerators to process a first workload to be received via a first path of communication through the circuit switch, the first path of communication based on a partitioned circuit switch topology that isolates the two or more accelerators from at least one other accelerator, the at least one other accelerator to process a second workload to be received via a second path of communication through the circuit switch; unlink an accelerator from among the two or more accelerators for the accelerator to process a third workload, the accelerator unlinked based on a different processing requirement for the third workload; configure the circuit switch to enable the accelerator to receive the third workload via a third path of communication through the circuit switch; and isolate the accelerator from the two or more accelerators based on the partitioned circuit switch topology.
- The apparatus of claim 1, the switching controller to link the two or more accelerators based on a processing requirement for the first workload, a configuration of accelerators to process the first workload, a memory requirement to process the first workload, an input/output requirement to process the first workload, or an amount of time in which the first workload must be processed.
- The apparatus of claim 1, wherein the circuit switch comprises an electrical circuit switch.
- The apparatus of claim 1, wherein the circuit switch comprises an optical circuit switch.
- The apparatus of claim 1, the switching controller to link the two or more accelerators based on the first workload having a higher priority than a different workload.
- The apparatus of claim 1, the switching controller to reconfigure the circuit switch such that the two or more accelerators process a different workload received via the first path of communication upon completion of processing the first workload.
- The apparatus of claim 1, the two or more accelerators or the at least one other accelerator comprising a graphics processing unit (GPU) or a field programmable gate array (FPGA).
- A non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed, enable processing circuitry to: select two or more accelerators to link; configure a circuit switch to link the two or more accelerators to process a first workload that is to be received via a first path of communication through the circuit switch, the first path of communication based on a partitioned circuit switch topology that isolates the two or more accelerators from at least one other accelerator, the at least one other accelerator to process a second workload to be received via a second path of communication through the circuit switch; unlink an accelerator from among the two or more accelerators for the accelerator to process a third workload, the accelerator unlinked based on a different processing requirement for the third workload; configure the circuit switch to enable the accelerator to receive the third workload via a third path of communication through the circuit switch; and isolate the accelerator from the two or more accelerators based on the partitioned circuit switch topology.
- The non-transitory computer-readable storage medium of claim 8, comprising a plurality of instructions, that when executed, enable processing circuitry to select the two or more accelerators based on a processing requirement for the first workload, a configuration of accelerators to process the first workload, a memory requirement to process the first workload, an input/output requirement to process the first workload, or an amount of time in which the first workload must be processed.
- The non-transitory computer-readable storage medium of claim 8, wherein the circuit switch comprises an electrical circuit switch.
- The non-transitory computer-readable storage medium of claim 8, wherein the circuit switch comprises an optical circuit switch.
- The non-transitory computer-readable storage medium of claim 8, comprising a plurality of instructions, that when executed, enable processing circuitry to link the two or more accelerators based on the first workload having a higher priority than a different workload.
- The non-transitory computer-readable storage medium of claim 8, comprising a plurality of instructions, that when executed, enable processing circuitry to reconfigure the circuit switch such that the two or more accelerators process a different workload received via the first path of communication upon completion of processing the first workload.
- A computer-implemented method, comprising: selecting two or more accelerators to link; configuring a circuit switch to link the two or more accelerators to process a first workload that is to be received via a first path of communication through the circuit switch, the first path of communication based on a partitioned circuit switch topology that isolates the two or more accelerators from at least one other accelerator, the at least one other accelerator to process a second workload to be received via a second path of communication through the circuit switch; unlinking an accelerator from among the two or more accelerators for the accelerator to process a third workload, the accelerator unlinked based on a different processing requirement for the third workload; configuring the circuit switch to enable the accelerator to receive the third workload via a third path of communication through the circuit switch; and isolating the accelerator from the two or more accelerators based on the partitioned circuit switch topology.
- The computer-implemented method of claim 14, comprising selecting the two or more accelerators based on a processing requirement for the first workload, a configuration of accelerators to process the first workload, a memory requirement to process the first workload, an input/output requirement to process the first workload, or an amount of time in which the first workload must be processed.
- The computer-implemented method of claim 14, wherein the circuit switch comprises an electrical circuit switch.
- The computer-implemented method of claim 14, wherein the circuit switch comprises an optical circuit switch.
- The computer-implemented method of claim 14, comprising linking the two or more accelerators based on the first workload having a higher priority than a different workload.
- The computer-implemented method of claim 14, comprising reconfiguring the circuit switch such that the two or more accelerators process a different workload received via the first path of communication upon completion of processing the first workload.
- The computer-implemented method of claim 14, the two or more accelerators comprising at least one of the two or more accelerators to be coupled with a memory device to facilitate processing of the first workload.
- The apparatus of claim 1, the two or more accelerators comprising at least one of the two or more accelerators to be coupled with a memory device to facilitate processing of the first workload.
- The apparatus of claim 21, comprising the at least one of the two or more accelerators to be coupled with the memory device to enable a central processing unit that couples with the circuit switch to access the memory device through the circuit switch in order to facilitate processing of the first workload.
- The apparatus of claim 1, the two or more accelerators comprising at least one of the two or more accelerators to be coupled with an input/output controller device to facilitate processing of the first workload.
- The apparatus of claim 23, comprising the at least one of the two or more accelerators to be coupled with the input/output controller device to enable a central processing unit that couples with the circuit switch to access the input/output controller device through the circuit switch in order to facilitate processing of the first workload.
- The non-transitory computer-readable storage medium of claim 8, the two or more accelerators comprising at least one of the two or more accelerators to be coupled with a memory device to facilitate processing of the first workload.
Description
This application claims priority to U.S. Provisional Patent Application No. 62/365,969, filed Jul. 22, 2016, U.S. Provisional Patent Application No. 62/376,859, filed Aug. 18, 2016, and U.S. Provisional Patent Application No. 62/427,268, filed Nov. 29, 2016, each of which are hereby incorporated by reference in their entirety.
Embodiments described herein generally include performing circuit switching for workloads.
A computing data center may include one or more computing systems including a plurality of compute nodes that may include various compute structures (e.g., servers or sleds) and may be physically located on multiple racks. The sleds may include a number of physical resources interconnected via one or more compute structures and buses. Typically, a computing data center may include a management entity to distribute workloads among the compute structures located within the racks. However, the management entity may currently distribute the workloads in a manner such that physical resources may be underutilized. For example, a workload may be distributed for processing on physical resources including four computer processing units. However, the same workload may be processed in two computer processing units and still meet the requirements of the workload. In this example, two of the computer processing units may have been able to process a different workload in parallel. Thus, embodiments may be directed to intelligently partitioning the physical resources without reducing bandwidth for inter-processor communications and maintaining dual paths of communication.
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Record as JSON
{
"publication_number": "US11184261B2",
"country": "US",
"kind": "B2",
"title": "Techniques to configure physical compute resources for workloads via circuit switching",
"abstract": "Embodiments are generally directed apparatuses, methods, techniques and so forth to select two or more processing units of the plurality of processing units to process a workload, and configure a circuit switch to link the two or more processing units to process the workload, the two or more processing units each linked to each other via paths of communication and the circuit switch.",
"claims": [
"1. An apparatus, comprising: a circuit switch; and a switching controller to: link two or more accelerators to process a first workload to be received via a first path of communication through the circuit switch, the first path of communication based on a partitioned circuit switch topology that isolates the two or more accelerators from at least one other accelerator, the at least one other accelerator to process a second workload to be received via a second path of communication through the circuit switch; unlink an accelerator from among the two or more accelerators for the accelerator to process a third workload, the accelerator unlinked based on a different processing requirement for the third workload; configure the circuit switch to enable the accelerator to receive the third workload via a third path of communication through the circuit switch; and isolate the accelerator from the two or more accelerators based on the partitioned circuit switch topology.",
"2. The apparatus of claim 1, the switching controller to link the two or more accelerators based on a processing requirement for the first workload, a configuration of accelerators to process the first workload, a memory requirement to process the first workload, an input/output requirement to process the first workload, or an amount of time in which the first workload must be processed.",
"3. The apparatus of claim 1, wherein the circuit switch comprises an electrical circuit switch.",
"4. The apparatus of claim 1, wherein the circuit switch comprises an optical circuit switch.",
"5. The apparatus of claim 1, the switching controller to link the two or more accelerators based on the first workload having a higher priority than a different workload.",
"6. The apparatus of claim 1, the switching controller to reconfigure the circuit switch such that the two or more accelerators process a different workload received via the first path of communication upon completion of processing the first workload.",
"7. The apparatus of claim 1, the two or more accelerators or the at least one other accelerator comprising a graphics processing unit (GPU) or a field programmable gate array (FPGA).",
"8. A non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed, enable processing circuitry to: select two or more accelerators to link; configure a circuit switch to link the two or more accelerators to process a first workload that is to be received via a first path of communication through the circuit switch, the first path of communication based on a partitioned circuit switch topology that isolates the two or more accelerators from at least one other accelerator, the at least one other accelerator to process a second workload to be received via a second path of communication through the circuit switch; unlink an accelerator from among the two or more accelerators for the accelerator to process a third workload, the accelerator unlinked based on a different processing requirement for the third workload; configure the circuit switch to enable the accelerator to receive the third workload via a third path of communication through the circuit switch; and isolate the accelerator from the two or more accelerators based on the partitioned circuit switch topology.",
"9. The non-transitory computer-readable storage medium of claim 8, comprising a plurality of instructions, that when executed, enable processing circuitry to select the two or more accelerators based on a processing requirement for the first workload, a configuration of accelerators to process the first workload, a memory requirement to process the first workload, an input/output requirement to process the first workload, or an amount of time in which the first workload must be processed.",
"10. The non-transitory computer-readable storage medium of claim 8, wherein the circuit switch comprises an electrical circuit switch.",
"11. The non-transitory computer-readable storage medium of claim 8, wherein the circuit switch comprises an optical circuit switch.",
"12. The non-transitory computer-readable storage medium of claim 8, comprising a plurality of instructions, that when executed, enable processing circuitry to link the two or more accelerators based on the first workload having a higher priority than a different workload.",
"13. The non-transitory computer-readable storage medium of claim 8, comprising a plurality of instructions, that when executed, enable processing circuitry to reconfigure the circuit switch such that the two or more accelerators process a different workload received via the first path of communication upon completion of processing the first workload.",
"14. A computer-implemented method, comprising: selecting two or more accelerators to link; configuring a circuit switch to link the two or more accelerators to process a first workload that is to be received via a first path of communication through the circuit switch, the first path of communication based on a partitioned circuit switch topology that isolates the two or more accelerators from at least one other accelerator, the at least one other accelerator to process a second workload to be received via a second path of communication through the circuit switch; unlinking an accelerator from among the two or more accelerators for the accelerator to process a third workload, the accelerator unlinked based on a different processing requirement for the third workload; configuring the circuit switch to enable the accelerator to receive the third workload via a third path of communication through the circuit switch; and isolating the accelerator from the two or more accelerators based on the partitioned circuit switch topology.",
"15. The computer-implemented method of claim 14, comprising selecting the two or more accelerators based on a processing requirement for the first workload, a configuration of accelerators to process the first workload, a memory requirement to process the first workload, an input/output requirement to process the first workload, or an amount of time in which the first workload must be processed.",
"16. The computer-implemented method of claim 14, wherein the circuit switch comprises an electrical circuit switch.",
"17. The computer-implemented method of claim 14, wherein the circuit switch comprises an optical circuit switch.",
"18. The computer-implemented method of claim 14, comprising linking the two or more accelerators based on the first workload having a higher priority than a different workload.",
"19. The computer-implemented method of claim 14, comprising reconfiguring the circuit switch such that the two or more accelerators process a different workload received via the first path of communication upon completion of processing the first workload.",
"20. The computer-implemented method of claim 14, the two or more accelerators comprising at least one of the two or more accelerators to be coupled with a memory device to facilitate processing of the first workload.",
"21. The apparatus of claim 1, the two or more accelerators comprising at least one of the two or more accelerators to be coupled with a memory device to facilitate processing of the first workload.",
"22. The apparatus of claim 21, comprising the at least one of the two or more accelerators to be coupled with the memory device to enable a central processing unit that couples with the circuit switch to access the memory device through the circuit switch in order to facilitate processing of the first workload.",
"23. The apparatus of claim 1, the two or more accelerators comprising at least one of the two or more accelerators to be coupled with an input/output controller device to facilitate processing of the first workload.",
"24. The apparatus of claim 23, comprising the at least one of the two or more accelerators to be coupled with the input/output controller device to enable a central processing unit that couples with the circuit switch to access the input/output controller device through the circuit switch in order to facilitate processing of the first workload.",
"25. The non-transitory computer-readable storage medium of claim 8, the two or more accelerators comprising at least one of the two or more accelerators to be coupled with a memory device to facilitate processing of the first workload."
],
"description_excerpt": "This application claims priority to U.S. Provisional Patent Application No. 62/365,969, filed Jul. 22, 2016, U.S. Provisional Patent Application No. 62/376,859, filed Aug. 18, 2016, and U.S. Provisional Patent Application No. 62/427,268, filed Nov. 29, 2016, each of which are hereby incorporated by reference in their entirety.\n\nEmbodiments described herein generally include performing circuit switching for workloads.\n\nA computing data center may include one or more computing systems including a plurality of compute nodes that may include various compute structures (e.g., servers or sleds) and may be physically located on multiple racks. The sleds may include a number of physical resources interconnected via one or more compute structures and buses. Typically, a computing data center may include a management entity to distribute workloads among the compute structures located within the racks. However, the management entity may currently distribute the workloads in a manner such that physical resources may be underutilized. For example, a workload may be distributed for processing on physical resources including four computer processing units. However, the same workload may be processed in two computer processing units and still meet the requirements of the workload. In this example, two of the computer processing units may have been able to process a different workload in parallel. Thus, embodiments may be directed to intelligently partitioning the physical resources without reducing bandwidth for inter-processor communications and maintaining dual paths of communication.",
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"assignees": [
"INTEL CORP"
],
"inventors": [
"NACHIMUTHU MURUGASAMY K",
"KUMAR MOHAN J"
],
"filing_date": "2016-12-31",
"publication_date": "2021-11-23",
"grant_date": "2021-11-23",
"priority_date": "2016-07-22",
"application_number": "US-201615396473-A",
"family_id": "60804962",
"citations": [
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}
Record 571 of 5,000 in Patents full text (MLC-0201). Request the full dataset.