MLchartDataset catalogue

Patent · US10390114B2 · B2 · US

Memory sharing for physical accelerator resources in a data center

(11) Publication number
US10390114B2
(21) Application number
15/394,281
(22) Filing date
2016-12-29
(30) Priority date
2016-07-22
(43) Publication date
2019-08-20
(45) Date of grant
2019-08-20
(51) IPC
B25J 15/00; B65G 1/04; G02B 6/38; G02B 6/42; G02B 6/44; G05D 23/19; G05D 23/20; G06F 1/18; G06F 11/14; G06F 11/34; G06F 12/0862; G06F 12/0893; G06F 12/10; G06F 12/109; G06F 12/14; G06F 13/16; G06F 13/40; G06F 13/42; G06F 15/80; G06F 16/901; G06F 3/06; G06F 8/65; G06F 9/4401; G06F 9/50; G06Q 10/00; G06Q 10/06; G06Q 10/08; G06Q 50/04; G07C 5/00; G08C 17/02; G11C 11/56; G11C 14/00; G11C 5/02; G11C 5/06; G11C 7/10; H03M 7/30; H03M 7/40; H04B 10/25; H04L 12/24; H04L 12/26; H04L 12/28; H04L 12/751; H04L 12/781; H04L 12/811; H04L 12/851; H04L 12/911; H04L 12/919; H04L 12/927; H04L 12/931; H04L 12/933; H04L 12/939; H04L 12/947; H04L 29/06; H04L 29/08; H04L 29/12; H04L 9/06; H04L 9/14; H04L 9/32; H04Q 1/04; H04Q 11/00; H04W 4/02; H04W 4/80; H05K 1/02; H05K 1/18; H05K 13/04; H05K 5/02; H05K 7/14; H05K 7/20
(52) CPC
  • G06F Electric digital data processing: 3/061, 1/183, 1/20, 11/141, 11/3414, 12/0862, 12/0893, 12/10, 12/109, 12/1408, 13/161, 13/1668, 13/1694, 13/385, 13/4022, 13/4068, 13/409, 13/42, 13/4282, 15/161, 15/8061, 16/1748, 16/9014, 2209/483, 2209/5019, 2209/5022, 2212/1008, 2212/1024, 2212/1041, 2212/1044, 2212/152, 2212/202, 2212/401, 2212/402, 2212/7207, 3/0611, 3/0613, 3/0616, 3/0619, 3/0625, 3/0631, 3/0638, 3/064, 3/0647, 3/065, 3/0653, 3/0655, 3/0658, 3/0659, 3/0664, 3/0665, 3/067, 3/0673, 3/0679, 3/0683, 3/0688, 3/0689, 8/65, 9/30036, 9/3887, 9/4401, 9/4881, 9/5016, 9/5027, 9/5044, 9/505, 9/5072, 9/5077, 9/544
  • B25J Manipulators; chambers provided with manipulation devices: 15/0014
  • B65G Transport or storage devices, e.g. conveyors for loading or tipping, shop conveyor systems or pneumatic tube conveyors: 1/0492
  • G02B Optical elements, systems or apparatus: 6/3882, 6/3893, 6/3897, 6/4292, 6/4452
  • G05D Systems for controlling or regulating non-electric variables: 23/1921, 23/2039
  • G06Q Information and communication technology [ICT] specially adapted for administrative, commercial, financial, managerial or supervisory purposes; systems or methods specially adapted for administrative, commercial, financial, managerial or supervisory purposes, not otherwise provided for: 10/06, 10/06314, 10/087, 10/20, 50/04
  • G07C Time or attendance registers; registering or indicating the working of machines; generating random numbers; voting or lottery apparatus; arrangements, systems or apparatus for checking not provided for elsewhere: 5/008
  • G08C Transmission systems for measured values, control or similar signals: 17/02, 2200/00
  • G11C Static stores: 11/56, 14/0009, 5/02, 5/06, 7/1072
  • H03M Coding; decoding; code conversion in general: 7/30, 7/3084, 7/3086, 7/40, 7/4031, 7/4056, 7/4081, 7/6005, 7/6023
  • H04B Transmission: 10/25, 10/2504, 10/25891
  • H04J Multiplex communication: 14/00
  • H04L Transmission of digital information, e.g. telegraphic communication: 12/2809, 29/12009, 41/024, 41/046, 41/0813, 41/082, 41/0896, 41/12, 41/145, 41/147, 41/149, 41/40, 41/5019, 43/065, 43/08, 43/0817, 43/0876, 43/0894, 43/16, 45/02, 45/52, 47/24, 47/38, 47/765, 47/782, 47/805, 47/82, 47/823, 47/83, 49/00, 49/15, 49/25, 49/35, 49/357, 49/45, 49/555, 61/00, 67/02, 67/10, 67/1004, 67/1008, 67/1012, 67/1014, 67/1029, 67/1034, 67/1097, 67/12, 67/16, 67/306, 67/34, 67/51, 69/04, 69/18, 69/329, 9/0643, 9/14, 9/3247, 9/3263
  • H04Q Selecting: 1/04, 1/09, 11/00, 11/0003, 11/0005, 11/0062, 11/0071, 2011/0037, 2011/0041, 2011/0052, 2011/0073, 2011/0079, 2011/0086, 2213/13523, 2213/13527
  • H04W Wireless communication networks: 4/023, 4/80
  • H05K Printed circuits; casings or constructional details of electric apparatus; manufacture of assemblages of electrical components: 1/0203, 1/181, 13/0486, 2201/066, 2201/10121, 2201/10159, 2201/10189, 5/0204, 7/1418, 7/1421, 7/1422, 7/1442, 7/1447, 7/1461, 7/1485, 7/1487, 7/1489, 7/1491, 7/1492, 7/1498, 7/2039, 7/20709, 7/20727, 7/20736, 7/20745, 7/20836
  • Y02D Climate change mitigation technologies in information and communication technologies [ICT], i.e. information and communication technologies aiming at the reduction of their own energy use: 10/00, 10/14, 10/151
  • Y02P Climate change mitigation technologies in the production or processing of goods: 90/30
  • Y04S Systems integrating technologies related to power network operation, communication or information technologies for improving the electrical power generation, transmission, distribution, management or usage, i.e. smart grids: 10/50, 10/52
  • Y10S Technical subjects covered by former uspc cross-reference art collections [xracs] and digests: 901/01, 901/30
(73) Assignee
Intel Corp
(72) Inventors
Mark A. Schmisseur
(54) Title
Memory sharing for physical accelerator resources in a data center
(57) Abstract

Examples may include sleds for a rack in a data center including physical accelerator resources and memory for the accelerator resources. The memory can be shared between the accelerator resources. One or more memory controllers can be provided to couple the accelerator resources to the memory to provide memory access to all the accelerator resources. Each accelerator resource can include a memory controller to access a portion of the memory while the accelerator resources can be coupled via an out-of-band channel to provide memory access to the other portions of the memory.

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Claims (24)

  1. A system for a data center comprising: a rack comprising a plurality of sled spaces; and at least one physical accelerator resource sled coupled to the rack via a one of the plurality of sled spaces, the sled comprising: a plurality of physical accelerator resources; a bank of physical memory; and one or more memory controllers to couple the bank of physical memory to each of the plurality of physical accelerator resources to provide each of the plurality of physical accelerator resources access to the bank of physical memory; the at least one physical accelerator resource sled comprising a first surface and a second surface different than the first surface, the plurality of physical accelerator resources disposed on the first surface and the bank of physical memory disposed on a second surface, the first surface and the second surface opposite from each other; the bank of physical memory having more than one groups of physical memory, the plurality of physical accelerator resources coupled with the more than one groups of physical memory via out-of-band (OOB) channels; the plurality of physical accelerator resources to access the more than one groups of physical memory via either direct attachment through the one or more memory controllers or via the OOB channels.
  2. The system of claim 1, the plurality of physical accelerator resources comprising field-programmable gate array (FPGA) packages.
  3. The system of claim 2, the plurality of physical accelerator resources comprising a first FPGA package and a second FPGA package, the first and the second FPGA packages to couple to the bank of physical memory through the one or more memory controllers.
  4. The system of claim 2, the plurality of physical accelerator resources comprising a first FPGA package and a second FPGA package and the one or more memory controllers comprising a first memory controller and a second memory controller, the first FPGA package to couple to the bank of physical memory through the first memory controller and the second FPGA package to couple to the bank of physical memory through the second memory controller.
  5. The system of claim 4, the bank of physical memory comprising at least a first group of the more than one groups of physical memory and a second group of the more than one groups of physical memory, the first FPGA package to couple to the first group of physical memory through the first memory controller and the second FPGA package to couple to the second group of physical memory through the second memory controller.
  6. The system of claim 5, comprising one of the OOB channels coupled to the first FPGA package and the second FPGA package, the first and the second FPGA packages to access the first or the second groups of physical memory via the one of the OOB channels.
  7. The system of claim 4, the first memory controller integrated into the first FPGA package and the second memory controller integrated into the second FPGA package.
  8. The system of claim 1, the bank of physical memory comprising a plurality of memory dual in-line memory modules.
  9. The system of claim 1, the bank of physical memory comprising a combination of dynamic random access memory and three-dimensional (3D) cross-point memory.
  10. An apparatus for a sled, comprising: a plurality of physical accelerator resources; a bank of physical memory; one or more memory controllers to couple the bank of physical memory to each of the plurality of physical accelerator resources to provide each of the plurality of physical accelerator resources access to the bank of physical memory; and a frame, the plurality of physical accelerator resources mounted to the frame in a first surface and the bank of physical memory mounted to the frame in a second surface, the first surface opposite from the second surface; the bank of physical memory having more than one groups of physical memory, the plurality of physical accelerator resources coupled with the more than one groups of physical memory via out-of-band (OOB) channels; the plurality of physical accelerator resources to access the more than one groups of physical memory via either direct attachment through the one or more memory controllers or via the OOB channels.
  11. The apparatus of claim 10, the plurality of physical accelerator resources comprising field-programmable gate array (FPGA) packages.
  12. The apparatus of claim 11, the plurality of physical accelerator resources comprising a first FPGA package and a second FPGA package, the first and the second FPGA packages to couple to the bank of physical memory through the one or more memory controllers.
  13. The apparatus of claim 11, the plurality of physical accelerator resources comprising a first FPGA package and a second FPGA package and the one or more memory controllers comprising a first memory controller and a second memory controller, the first FPGA package to couple to the bank of physical memory through the first memory controller and the second FPGA package to couple to the bank of physical memory through the second memory controller.
  14. The apparatus of claim 13, the bank of physical memory comprising at least a first group of the more than one groups of physical memory and a second group of the more than one groups of physical memory, the first FPGA package to couple to the first group of physical memory through the first memory controller and the second FPGA package to couple to the second group of physical memory through the second memory controller, the apparatus comprising one of the OOB channels coupled to the first FPGA package and the second FPGA package, the first and the second FPGA packages to access the first or the second groups of physical memory via the one of the OOB channels.
  15. The apparatus of claim 13, the first memory controller integrated into the first FPGA package and the second memory controller integrated into the second FPGA package.
  16. The apparatus of claim 10, comprising the frame mountable within a sled space of a rack of a data center, the plurality of physical accelerator resources, the bank of physical memory, and the one or more memory controllers mounted to the frame.
  17. The apparatus of claim 10, the bank of physical memory comprising a combination of dynamic random access memory and three-dimensional (3D) cross-point memory.
  18. An apparatus comprising: a frame mountable within a sled space of a rack of a data center; a plurality of physical accelerator resources coupled to the frame; and a plurality of sockets to receive physical memory modules; the plurality of physical accelerator resources mounted to the frame in a first surface and the plurality of sockets mounted to the frame in a second surface, the first surface opposite from the second surface; the physical memory modules to comprise more than one groups of physical memory, the plurality of physical accelerator resources coupled with the plurality of sockets to couple with the more than one groups of physical memory via out-of-band (OOB) channels; the plurality of physical accelerator resources to access the more than one groups of physical memory via either direct attachment through one or more memory controllers or via the OOB channels.
  19. The apparatus of claim 18, the plurality of physical accelerator resources comprising a first field-programmable gate array (FPGA) package and a second FPGA package and the one or more memory controllers comprising a first memory controller and a second memory controller, the first FPGA package to couple to the physical memory modules through the first memory controller and the second FPGA package to couple to the physical memory modules through the second memory controller.
  20. The apparatus of claim 19, the plurality of sockets comprising at least a first group of sockets and a second group of sockets, the first FPGA package to couple to a first group of the more than one groups of physical memory modules coupled to the first group of sockets through the first memory controller and the second FPGA package to couple to a second group of the more than one groups of physical memory modules coupled to the second group of sockets through the second memory controller.
  21. The apparatus of claim 18, the plurality of sockets arranged to receive a combination of dynamic random access memory and three-dimensional (3D) cross-point memory.
  22. The apparatus of claim 18, the plurality of physical accelerator resources comprising field-programmable gate array (FPGA) packages.
  23. The apparatus of claim 22, wherein the FPGA packages comprise the one or more memory controllers to couple the physical memory modules to each of the plurality of physical accelerator resources to provide each of the plurality of physical accelerator resources memory access.
  24. The apparatus of claim 22, further comprising the one or more memory controllers coupled with the plurality of physical accelerator resources to couple the physical memory modules to each of the plurality of physical accelerator resources to provide each of the plurality of physical accelerator resources memory access.

Description

This application claims priority to United States Provisional Patent Application entitled “Framework and Techniques for Pools of Configurable Computing Resources” filed on Nov. 29, 2016 and assigned Ser. No. 62/427,268; United States Provisional Patent Application entitled “Scalable System Framework Prime (SSFP) Omnibus Provisional II” filed on Aug. 18, 2016 and assigned Ser. No. 62/376,859; and United States Provisional Patent Application entitled “Framework and Techniques for Pools of Configurable Computing Resources” filed on Jul. 22, 2016 and assigned Ser. No. 62/365,969, each of which is hereby incorporated by reference in their entirety.

Embodiments described herein generally relate to data centers and particularly to accelerator resources within a data center.

Advancements in networking have enabled the rise in pools of physical resources. A pool of physical resources may be formed from a physical infrastructure including disaggregate physical resources, such as, for example, compute and storage resources found in large data centers. The physical infrastructure can include a number of computing systems having processors, memory, storage, networking, power, cooling, etc. Management entities of these data centers can aggregate a selection of the physical resources to form servers and/or physical computing hosts. These hosts can subsequently be allocated to execute system SW (e.g., OSs, VMMs, or the like) and host containers, VMs, and/or applications.

FIG. 1 illustrates a first example data center.

Citations (6)

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  • US8285927B2
  • US20150334867A1
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Record as JSON 
{
  "publication_number": "US10390114B2",
  "country": "US",
  "kind": "B2",
  "title": "Memory sharing for physical accelerator resources in a data center",
  "abstract": "Examples may include sleds for a rack in a data center including physical accelerator resources and memory for the accelerator resources. The memory can be shared between the accelerator resources. One or more memory controllers can be provided to couple the accelerator resources to the memory to provide memory access to all the accelerator resources. Each accelerator resource can include a memory controller to access a portion of the memory while the accelerator resources can be coupled via an out-of-band channel to provide memory access to the other portions of the memory.",
  "claims": [
    "1. A system for a data center comprising: a rack comprising a plurality of sled spaces; and at least one physical accelerator resource sled coupled to the rack via a one of the plurality of sled spaces, the sled comprising: a plurality of physical accelerator resources; a bank of physical memory; and one or more memory controllers to couple the bank of physical memory to each of the plurality of physical accelerator resources to provide each of the plurality of physical accelerator resources access to the bank of physical memory; the at least one physical accelerator resource sled comprising a first surface and a second surface different than the first surface, the plurality of physical accelerator resources disposed on the first surface and the bank of physical memory disposed on a second surface, the first surface and the second surface opposite from each other; the bank of physical memory having more than one groups of physical memory, the plurality of physical accelerator resources coupled with the more than one groups of physical memory via out-of-band (OOB) channels; the plurality of physical accelerator resources to access the more than one groups of physical memory via either direct attachment through the one or more memory controllers or via the OOB channels.",
    "2. The system of claim 1, the plurality of physical accelerator resources comprising field-programmable gate array (FPGA) packages.",
    "3. The system of claim 2, the plurality of physical accelerator resources comprising a first FPGA package and a second FPGA package, the first and the second FPGA packages to couple to the bank of physical memory through the one or more memory controllers.",
    "4. The system of claim 2, the plurality of physical accelerator resources comprising a first FPGA package and a second FPGA package and the one or more memory controllers comprising a first memory controller and a second memory controller, the first FPGA package to couple to the bank of physical memory through the first memory controller and the second FPGA package to couple to the bank of physical memory through the second memory controller.",
    "5. The system of claim 4, the bank of physical memory comprising at least a first group of the more than one groups of physical memory and a second group of the more than one groups of physical memory, the first FPGA package to couple to the first group of physical memory through the first memory controller and the second FPGA package to couple to the second group of physical memory through the second memory controller.",
    "6. The system of claim 5, comprising one of the OOB channels coupled to the first FPGA package and the second FPGA package, the first and the second FPGA packages to access the first or the second groups of physical memory via the one of the OOB channels.",
    "7. The system of claim 4, the first memory controller integrated into the first FPGA package and the second memory controller integrated into the second FPGA package.",
    "8. The system of claim 1, the bank of physical memory comprising a plurality of memory dual in-line memory modules.",
    "9. The system of claim 1, the bank of physical memory comprising a combination of dynamic random access memory and three-dimensional (3D) cross-point memory.",
    "10. An apparatus for a sled, comprising: a plurality of physical accelerator resources; a bank of physical memory; one or more memory controllers to couple the bank of physical memory to each of the plurality of physical accelerator resources to provide each of the plurality of physical accelerator resources access to the bank of physical memory; and a frame, the plurality of physical accelerator resources mounted to the frame in a first surface and the bank of physical memory mounted to the frame in a second surface, the first surface opposite from the second surface; the bank of physical memory having more than one groups of physical memory, the plurality of physical accelerator resources coupled with the more than one groups of physical memory via out-of-band (OOB) channels; the plurality of physical accelerator resources to access the more than one groups of physical memory via either direct attachment through the one or more memory controllers or via the OOB channels.",
    "11. The apparatus of claim 10, the plurality of physical accelerator resources comprising field-programmable gate array (FPGA) packages.",
    "12. The apparatus of claim 11, the plurality of physical accelerator resources comprising a first FPGA package and a second FPGA package, the first and the second FPGA packages to couple to the bank of physical memory through the one or more memory controllers.",
    "13. The apparatus of claim 11, the plurality of physical accelerator resources comprising a first FPGA package and a second FPGA package and the one or more memory controllers comprising a first memory controller and a second memory controller, the first FPGA package to couple to the bank of physical memory through the first memory controller and the second FPGA package to couple to the bank of physical memory through the second memory controller.",
    "14. The apparatus of claim 13, the bank of physical memory comprising at least a first group of the more than one groups of physical memory and a second group of the more than one groups of physical memory, the first FPGA package to couple to the first group of physical memory through the first memory controller and the second FPGA package to couple to the second group of physical memory through the second memory controller, the apparatus comprising one of the OOB channels coupled to the first FPGA package and the second FPGA package, the first and the second FPGA packages to access the first or the second groups of physical memory via the one of the OOB channels.",
    "15. The apparatus of claim 13, the first memory controller integrated into the first FPGA package and the second memory controller integrated into the second FPGA package.",
    "16. The apparatus of claim 10, comprising the frame mountable within a sled space of a rack of a data center, the plurality of physical accelerator resources, the bank of physical memory, and the one or more memory controllers mounted to the frame.",
    "17. The apparatus of claim 10, the bank of physical memory comprising a combination of dynamic random access memory and three-dimensional (3D) cross-point memory.",
    "18. An apparatus comprising: a frame mountable within a sled space of a rack of a data center; a plurality of physical accelerator resources coupled to the frame; and a plurality of sockets to receive physical memory modules; the plurality of physical accelerator resources mounted to the frame in a first surface and the plurality of sockets mounted to the frame in a second surface, the first surface opposite from the second surface; the physical memory modules to comprise more than one groups of physical memory, the plurality of physical accelerator resources coupled with the plurality of sockets to couple with the more than one groups of physical memory via out-of-band (OOB) channels; the plurality of physical accelerator resources to access the more than one groups of physical memory via either direct attachment through one or more memory controllers or via the OOB channels.",
    "19. The apparatus of claim 18, the plurality of physical accelerator resources comprising a first field-programmable gate array (FPGA) package and a second FPGA package and the one or more memory controllers comprising a first memory controller and a second memory controller, the first FPGA package to couple to the physical memory modules through the first memory controller and the second FPGA package to couple to the physical memory modules through the second memory controller.",
    "20. The apparatus of claim 19, the plurality of sockets comprising at least a first group of sockets and a second group of sockets, the first FPGA package to couple to a first group of the more than one groups of physical memory modules coupled to the first group of sockets through the first memory controller and the second FPGA package to couple to a second group of the more than one groups of physical memory modules coupled to the second group of sockets through the second memory controller.",
    "21. The apparatus of claim 18, the plurality of sockets arranged to receive a combination of dynamic random access memory and three-dimensional (3D) cross-point memory.",
    "22. The apparatus of claim 18, the plurality of physical accelerator resources comprising field-programmable gate array (FPGA) packages.",
    "23. The apparatus of claim 22, wherein the FPGA packages comprise the one or more memory controllers to couple the physical memory modules to each of the plurality of physical accelerator resources to provide each of the plurality of physical accelerator resources memory access.",
    "24. The apparatus of claim 22, further comprising the one or more memory controllers coupled with the plurality of physical accelerator resources to couple the physical memory modules to each of the plurality of physical accelerator resources to provide each of the plurality of physical accelerator resources memory access."
  ],
  "description_excerpt": "This application claims priority to United States Provisional Patent Application entitled “Framework and Techniques for Pools of Configurable Computing Resources” filed on Nov. 29, 2016 and assigned Ser. No. 62/427,268; United States Provisional Patent Application entitled “Scalable System Framework Prime (SSFP) Omnibus Provisional II” filed on Aug. 18, 2016 and assigned Ser. No. 62/376,859; and United States Provisional Patent Application entitled “Framework and Techniques for Pools of Configurable Computing Resources” filed on Jul. 22, 2016 and assigned Ser. No. 62/365,969, each of which is hereby incorporated by reference in their entirety.\n\nEmbodiments described herein generally relate to data centers and particularly to accelerator resources within a data center.\n\nAdvancements in networking have enabled the rise in pools of physical resources. A pool of physical resources may be formed from a physical infrastructure including disaggregate physical resources, such as, for example, compute and storage resources found in large data centers. The physical infrastructure can include a number of computing systems having processors, memory, storage, networking, power, cooling, etc. Management entities of these data centers can aggregate a selection of the physical resources to form servers and/or physical computing hosts. These hosts can subsequently be allocated to execute system SW (e.g., OSs, VMMs, or the like) and host containers, VMs, and/or applications.\n\nFIG. 1 illustrates a first example data center.",
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  ],
  "assignees": [
    "Intel Corp"
  ],
  "inventors": [
    "Mark A. Schmisseur"
  ],
  "filing_date": "2016-12-29",
  "publication_date": "2019-08-20",
  "grant_date": "2019-08-20",
  "priority_date": "2016-07-22",
  "application_number": "US-201615394281-A",
  "family_id": "60804962",
  "cited_by_count": 19,
  "citations": [
    "US7512728B2",
    "US8285927B2",
    "US20150334867A1",
    "US20140237284A1",
    "US20140351811A1",
    "US20160306667A1"
  ]
}

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