Patent · US11336547B2 · B2 · US
Technologies for dynamically managing resources in disaggregated accelerators
- (11) Publication number
- US11336547B2
- (21) Application number
- 17/235,135
- (22) Filing date
- 2021-04-20
- (30) Priority date
- 2016-07-22
- (43) Publication date
- 2022-05-17
- (45) Date of grant
- 2022-05-17
- (51) IPC
- B25J 15/00; B65G 1/04; G02B 6/38; G02B 6/42; G02B 6/44; G05D 23/19; G05D 23/20; G06F 1/18; G06F 1/20; G06F 11/14; G06F 11/34; G06F 12/0862; G06F 12/0893; G06F 12/10; G06F 12/109; G06F 12/14; G06F 13/16; G06F 13/40; G06F 13/42; G06F 15/16; G06F 15/80; G06F 16/901; G06F 3/06; G06F 8/65; G06F 9/30; G06F 9/38; G06F 9/4401; G06F 9/50; G06F 9/54; G06Q 10/00; G06Q 10/06; G06Q 10/08; G06Q 50/04; G07C 5/00; G08C 17/02; G11C 11/56; G11C 14/00; G11C 5/02; G11C 5/06; G11C 7/10; H03M 7/30; H03M 7/40; H04B 10/25; H04J 14/00; H04L 12/28; H04L 41/02; H04L 41/046; H04L 41/0813; H04L 41/082; H04L 41/0896; H04L 41/12; H04L 41/14; H04L 41/147; H04L 41/5019; H04L 43/065; H04L 43/08; H04L 43/0817; H04L 43/0876; H04L 43/0894; H04L 43/16; H04L 45/02; H04L 45/52; H04L 47/24; H04L 47/38; H04L 47/70; H04L 47/765; H04L 47/78; H04L 47/80; H04L 47/83; H04L 49/00; H04L 49/15; H04L 49/25; H04L 49/356; H04L 49/45; H04L 49/55; H04L 61/00; H04L 67/00; H04L 67/02; H04L 67/10; H04L 67/1004; H04L 67/1008; H04L 67/1012; H04L 67/1014; H04L 67/1029; H04L 67/1034; H04L 67/1097; H04L 67/12; H04L 67/306; H04L 67/51; H04L 69/04; H04L 69/329; H04L 9/06; H04L 9/14; H04L 9/32; H04Q 1/04; H04Q 11/00; H04W 4/02; H04W 4/80; H05K 1/02; H05K 1/18; H05K 13/04; H05K 5/02; H05K 7/14; H05K 7/20
- (52) CPC
- G06F Electric digital data processing: 3/061, 1/183, 1/20, 11/141, 11/3414, 12/0862, 12/0893, 12/10, 12/109, 12/1408, 13/161, 13/1668, 13/1694, 13/385, 13/4022, 13/4068, 13/409, 13/42, 13/4282, 15/161, 15/8061, 16/1748, 16/9014, 2209/483, 2209/5019, 2209/5022, 2212/1008, 2212/1024, 2212/1041, 2212/1044, 2212/152, 2212/202, 2212/401, 2212/402, 2212/7207, 3/0611, 3/0613, 3/0616, 3/0619, 3/0625, 3/0631, 3/0638, 3/064, 3/0647, 3/065, 3/0653, 3/0655, 3/0658, 3/0659, 3/0664, 3/0665, 3/067, 3/0673, 3/0679, 3/0683, 3/0688, 3/0689, 8/65, 9/30036, 9/3887, 9/4401, 9/4881, 9/5016, 9/5027, 9/5044, 9/505, 9/5072, 9/5077, 9/544
- B25J Manipulators; chambers provided with manipulation devices: 15/0014
- B65G Transport or storage devices, e.g. conveyors for loading or tipping, shop conveyor systems or pneumatic tube conveyors: 1/0492
- G02B Optical elements, systems or apparatus: 6/3882, 6/3893, 6/3897, 6/4292, 6/4452
- G05D Systems for controlling or regulating non-electric variables: 23/1921, 23/2039
- G06Q Information and communication technology [ICT] specially adapted for administrative, commercial, financial, managerial or supervisory purposes; systems or methods specially adapted for administrative, commercial, financial, managerial or supervisory purposes, not otherwise provided for: 10/06, 10/06314, 10/087, 10/20, 50/04
- G07C Time or attendance registers; registering or indicating the working of machines; generating random numbers; voting or lottery apparatus; arrangements, systems or apparatus for checking not provided for elsewhere: 5/008
- G08C Transmission systems for measured values, control or similar signals: 17/02, 2200/00
- G11C Static stores: 11/56, 14/0009, 5/02, 5/06, 7/1072
- H03M Coding; decoding; code conversion in general: 7/30, 7/3084, 7/3086, 7/40, 7/4031, 7/4056, 7/4081, 7/6005, 7/6023
- H04B Transmission: 10/25, 10/25891
- H04J Multiplex communication: 14/00
- H04L Transmission of digital information, e.g. telegraphic communication: 12/2809, 29/12009, 41/024, 41/046, 41/0813, 41/082, 41/0896, 41/12, 41/145, 41/147, 41/149, 41/40, 41/5019, 43/065, 43/08, 43/0817, 43/0876, 43/0894, 43/16, 45/02, 45/52, 47/24, 47/38, 47/765, 47/782, 47/805, 47/82, 47/823, 47/83, 49/00, 49/15, 49/25, 49/35, 49/357, 49/45, 49/555, 61/00, 67/02, 67/10, 67/1004, 67/1008, 67/1012, 67/1014, 67/1029, 67/1034, 67/1097, 67/12, 67/16, 67/306, 67/34, 67/51, 69/04, 69/18, 69/329, 9/0643, 9/14, 9/3247, 9/3263
- H04Q Selecting: 1/04, 1/09, 11/00, 11/0003, 11/0005, 11/0062, 11/0071, 2011/0037, 2011/0041, 2011/0052, 2011/0073, 2011/0079, 2011/0086, 2213/13523, 2213/13527
- H04W Wireless communication networks: 4/023, 4/80
- H05K Printed circuits; casings or constructional details of electric apparatus; manufacture of assemblages of electrical components: 1/0203, 1/181, 13/0486, 2201/066, 2201/10121, 2201/10159, 2201/10189, 5/0204, 7/1418, 7/1421, 7/1422, 7/1442, 7/1447, 7/1461, 7/1485, 7/1487, 7/1489, 7/1491, 7/1492, 7/1498, 7/2039, 7/20709, 7/20727, 7/20736, 7/20745, 7/20836
- Y02D Climate change mitigation technologies in information and communication technologies [ICT], i.e. information and communication technologies aiming at the reduction of their own energy use: 10/00
- Y02P Climate change mitigation technologies in the production or processing of goods: 90/30
- Y04S Systems integrating technologies related to power network operation, communication or information technologies for improving the electrical power generation, transmission, distribution, management or usage, i.e. smart grids: 10/50, 10/52
- Y10S Technical subjects covered by former uspc cross-reference art collections [xracs] and digests: 901/01, 901/30
- (73) Assignee
- Intel Corp
- (72) Inventors
- Francesc Guim Bernat; Susanne M. Balle; Rahul Khanna; Sujoy Sen; Karthik Kumar
- (54) Title
- Technologies for dynamically managing resources in disaggregated accelerators
- (57) Abstract
Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.
- Full text
- View on Google Patents
Claims (28)
- An accelerator device comprising: a field programmable gate array (FPGA) that includes multiple logic portions capable of separately executing a respective workload associated with respective separate application; at least one shared resource for use by the multiple logic portions to separately execute respective workloads; communication circuitry to receive a first workload from a first compute device, the first workload to be executed by a first logic portion of the multiple logic portions; and resource allocation circuitry to; identify a first resource utilization amount associated with the at least one shared resource to be used by the first logic portion to execute the first workload, limit, as a function of the first resource utilization amount, a utilization of the at least one shared resource by the first logic portion to not exceed the first resource utilization amount as the first logic portion executes the first workload, and adjust the first resource utilization amount to a second resource utilization amount as the first workload is executed by the first logic portion.
- The accelerator device of claim 1, further comprising a resource monitor circuitry to monitor the utilization of the at least one shared resource by the first logic portion as the first workload is executed and report the utilization to a second compute device.
- The accelerator device of claim 2, wherein the resource monitor circuitry is further to determine whether the utilization of the at least one shared resource satisfies the first resource utilization amount and wherein to report the utilization to second compute device comprises to report the utilization in response to a determination that the utilization does not satisfy the first resource utilization amount.
- The accelerator device of claim 3, wherein to adjust the first resource utilization amount comprises to: receive an adjustment to the first resource utilization amount from the second compute device; and apply the adjustment to the first resource utilization amount to determine the second resource utilization amount.
- The accelerator device of claim 1, wherein to receive the first workload comprises to receive a bit stream indicative of the first workload to be accelerated.
- The accelerator device of claim 1, wherein to receive the first workload comprises to receive a designation of a logic portion to execute the first workload.
- The accelerator device of claim 1, wherein to identify the first resource utilization amount comprises to receive a resource utilization amount indicative of an amount of memory to be used by the first logic portion, the memory to include dynamic random access memory.
- The accelerator device of claim 1, wherein to identify the first resource utilization amount comprises to receive a resource utilization amount indicative of an amount of data storage to be used by the first logic portion.
- The accelerator device of claim 1, wherein to identify the first resource utilization amount comprises to receive a resource utilization amount of an amount of network bandwidth to be used by the first logic portion.
- The accelerator device of claim 1, wherein to identify the first resource utilization amount comprises to receive an identifier of a class of service associated with an amount of a resource to be used by the first logic portion.
- The accelerator device of claim 1, further comprising: the communication circuitry to receive a second workload associated with a second application, the second workload to be executed by a second logic portion of the multiple logic portions; and the resource allocation circuitry to; identify a third resource utilization amount associated with the at least one shared resource to be used by the second logic portion to execute the second workload, limit, as a function of the third resource utilization amount, a utilization of the at least one shared resource by the second logic portion to not exceed the third resource utilization amount as the second logic portion executes the second workload, and adjust the third resource utilization amount to a fourth resource utilization amount as the second workload is executed by the second logic portion.
- One or more non-transitory machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause an accelerator device to: receive a first workload to be executed by a first logic portion of a plurality of logic portions of a field programmable gate array (FPGA) of the accelerator device, the plurality of logic portions capable of separately executing a respective workload; identify a first resource utilization amount associated with at least one shared resource of the accelerator device to be used by the first logic portion to execute the first workload; limit, as a function of the first resource utilization amount, a utilization of the at least one shared resource by the first logic portion to not exceed the first resource utilization amount as the first logic portion executes the first workload; and adjust, subsequent to the limiting of the utilization, the first resource utilization amount to a second resource utilization amount as the first workload is executed by the first logic portion.
- The one or more non-transitory machine-readable storage media of claim 12, wherein the plurality of instructions, when executed, further cause the accelerator device to: monitor the utilization of the at least one shared resource by the first logic portion as the first workload is executed; and report the utilization to a compute device.
- The one or more non-transitory machine-readable storage media of claim 13, wherein the plurality of instructions, when executed, further cause the accelerator device to: determine whether the utilization of the at least one shared resource satisfies the first resource utilization amount; wherein to report the utilization to the compute device comprises to report the utilization in response to a determination that the utilization does not satisfy the first resource utilization amount.
- The one or more non-transitory machine-readable storage media of claim 14, to adjust the first resource utilization amount comprises to: receive an adjustment to the first resource utilization amount from the compute device; and apply the adjustment to the first resource utilization amount to determine the second resource utilization amount.
- The one or more non-transitory machine-readable storage media of claim 14, wherein to receive the first workload comprises to receive a designation of a logic portion to execute the first workload.
- The one or more non-transitory machine-readable storage media of claim 12, wherein to receive the first workload comprises to receive a bit stream indicative of the first workload to be accelerated.
- The one or more non-transitory machine-readable storage media of claim 12, wherein to identify the first resource utilization amount comprises to receive resource utilization data indicative of the first resource utilization amount from an orchestrator server.
- The one or more non-transitory machine-readable storage media of claim 12, wherein to identify the first resource utilization amount comprises to receive resource utilization data indicative of the first resource utilization amount from a processor of a first compute device that is assigned to execute a portion of the first workload.
- The one or more non-transitory machine-readable storage media of claim 12, wherein to identify the first resource utilization amount comprises to receive a resource utilization amount indicative of an amount of memory to be used by the first logic portion, the memory to include dynamic random access memory.
- The one or more non-transitory machine-readable storage media of claim 12, wherein to identify the first resource utilization amount comprises to receive a resource utilization amount indicative of an amount of data storage to be used by the first logic portion.
- The one or more non-transitory machine-readable storage media of claim 12, wherein to identify the first resource utilization amount comprises to receive a resource utilization amount of an amount of network bandwidth to be used by the first logic portion.
- The one or more non-transitory machine-readable storage media of claim 12, wherein to identify the first resource utilization amount comprises to receive an identifier of a class of service associated with an amount of a resource to be used by the first logic portion.
- The one or more non-transitory machine-readable storage media of claim 12, wherein the plurality of instructions, when executed, further cause the accelerator device to: receive a second workload associated with a second application, the second workload to be executed by a second logic portion of the plurality of logic portions; identify a third resource utilization amount associated with the at least one shared resource to be used by the second logic portion to execute the second workload, limit, as a function of the third resource utilization amount, a utilization of the at least one shared resource by the second logic portion to not exceed the third resource utilization amount as the second logic portion executes the second workload, and adjust the third resource utilization amount to a fourth resource utilization amount as the second workload is executed by the second logic portion.
- A method comprising: receiving, by an accelerator device, a first workload associated with a first application, the first workload to be executed by a first logic portion of a plurality of logic portions of a field programmable gate array (FPGA) of the accelerator device, the plurality of logic portions capable of separately executing a respective workload; identifying a first resource utilization amount associated with at least one shared resource of the accelerator device to be used by the first logic portion to execute the first workload; limiting, as a function of the first resource utilization amount, a utilization of the at least one shared resource by the first logic portion to not exceed the first resource utilization amount as the first logic portion executes the first workload; and adjusting, subsequent to the limiting of the utilization, the first resource utilization amount to a second resource utilization amount as the first workload is executed by the first logic portion.
- The method of claim 25, further comprising: monitoring the utilization of the at least one shared resource by the first logic portion as the first workload is executed; and reporting the utilization to a computing device.
- The method of claim 26, further comprising: determining whether the utilization of the at least one shared resource satisfies the first resource utilization amount; wherein reporting utilization to the computing device comprises to report the utilization in response to a determination that the utilization does not satisfy the first resource utilization amount.
- The method of claim 25, further comprising: receiving a second workload associated with a second application, the second workload to be executed by a second logic portion of the plurality of logic portions; identifying a third resource utilization amount associated with the at least one shared resource to be used by the second logic portion to execute the second workload, limiting, as a function of the third resource utilization amount, a utilization of the at least one shared resource by the second logic portion to not exceed the third resource utilization amount as the second logic portion executes the second workload, and adjusting the third resource utilization amount to a fourth resource utilization amount as the second workload is executed by the second logic portion.
Description
Typical architectures for accelerator devices such as field programmable gate arrays (FPGAs), cryptography accelerators, graphics accelerators, and/or compression accelerators (referred to herein as “accelerators” or “accelerator resources”) capable of accelerating the execution of a set of operations in a workload (e.g., processes, applications, services, etc.) may allow static assignment of specified amounts of shared resources of the accelerator device (e.g., high bandwidth memory, data storage, etc.) among different portions of the logic (e.g., circuitry) of the accelerator device. Each logic portion may execute a separate set of operations to be accelerated, such as on behalf of different customers of a cloud data center. The resource needs of the logic portions may change as their workloads are executed, such that while a particular logic portion may be allocated 60% of the available high bandwidth memory, it only uses 30% of the high bandwidth memory during certain phases of the workload. During those phases, other logic portions of the accelerator device that might benefit from using more of the high bandwidth memory are prevented from doing so, as the allocations are statically defined. Changing the allocation of shared resources among the logic portions of the accelerator device typically involves stopping the execution of the workloads and reconfiguring the logic portions to use different amounts of the shared resources, and then resuming operation of the workloads.
Citations (7)
- US20120233488A1
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Record as JSON
{
"publication_number": "US11336547B2",
"country": "US",
"kind": "B2",
"title": "Technologies for dynamically managing resources in disaggregated accelerators",
"abstract": "Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.",
"claims": [
"1. An accelerator device comprising: a field programmable gate array (FPGA) that includes multiple logic portions capable of separately executing a respective workload associated with respective separate application; at least one shared resource for use by the multiple logic portions to separately execute respective workloads; communication circuitry to receive a first workload from a first compute device, the first workload to be executed by a first logic portion of the multiple logic portions; and resource allocation circuitry to; identify a first resource utilization amount associated with the at least one shared resource to be used by the first logic portion to execute the first workload, limit, as a function of the first resource utilization amount, a utilization of the at least one shared resource by the first logic portion to not exceed the first resource utilization amount as the first logic portion executes the first workload, and adjust the first resource utilization amount to a second resource utilization amount as the first workload is executed by the first logic portion.",
"2. The accelerator device of claim 1, further comprising a resource monitor circuitry to monitor the utilization of the at least one shared resource by the first logic portion as the first workload is executed and report the utilization to a second compute device.",
"3. The accelerator device of claim 2, wherein the resource monitor circuitry is further to determine whether the utilization of the at least one shared resource satisfies the first resource utilization amount and wherein to report the utilization to second compute device comprises to report the utilization in response to a determination that the utilization does not satisfy the first resource utilization amount.",
"4. The accelerator device of claim 3, wherein to adjust the first resource utilization amount comprises to: receive an adjustment to the first resource utilization amount from the second compute device; and apply the adjustment to the first resource utilization amount to determine the second resource utilization amount.",
"5. The accelerator device of claim 1, wherein to receive the first workload comprises to receive a bit stream indicative of the first workload to be accelerated.",
"6. The accelerator device of claim 1, wherein to receive the first workload comprises to receive a designation of a logic portion to execute the first workload.",
"7. The accelerator device of claim 1, wherein to identify the first resource utilization amount comprises to receive a resource utilization amount indicative of an amount of memory to be used by the first logic portion, the memory to include dynamic random access memory.",
"8. The accelerator device of claim 1, wherein to identify the first resource utilization amount comprises to receive a resource utilization amount indicative of an amount of data storage to be used by the first logic portion.",
"9. The accelerator device of claim 1, wherein to identify the first resource utilization amount comprises to receive a resource utilization amount of an amount of network bandwidth to be used by the first logic portion.",
"10. The accelerator device of claim 1, wherein to identify the first resource utilization amount comprises to receive an identifier of a class of service associated with an amount of a resource to be used by the first logic portion.",
"11. The accelerator device of claim 1, further comprising: the communication circuitry to receive a second workload associated with a second application, the second workload to be executed by a second logic portion of the multiple logic portions; and the resource allocation circuitry to; identify a third resource utilization amount associated with the at least one shared resource to be used by the second logic portion to execute the second workload, limit, as a function of the third resource utilization amount, a utilization of the at least one shared resource by the second logic portion to not exceed the third resource utilization amount as the second logic portion executes the second workload, and adjust the third resource utilization amount to a fourth resource utilization amount as the second workload is executed by the second logic portion.",
"12. One or more non-transitory machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause an accelerator device to: receive a first workload to be executed by a first logic portion of a plurality of logic portions of a field programmable gate array (FPGA) of the accelerator device, the plurality of logic portions capable of separately executing a respective workload; identify a first resource utilization amount associated with at least one shared resource of the accelerator device to be used by the first logic portion to execute the first workload; limit, as a function of the first resource utilization amount, a utilization of the at least one shared resource by the first logic portion to not exceed the first resource utilization amount as the first logic portion executes the first workload; and adjust, subsequent to the limiting of the utilization, the first resource utilization amount to a second resource utilization amount as the first workload is executed by the first logic portion.",
"13. The one or more non-transitory machine-readable storage media of claim 12, wherein the plurality of instructions, when executed, further cause the accelerator device to: monitor the utilization of the at least one shared resource by the first logic portion as the first workload is executed; and report the utilization to a compute device.",
"14. The one or more non-transitory machine-readable storage media of claim 13, wherein the plurality of instructions, when executed, further cause the accelerator device to: determine whether the utilization of the at least one shared resource satisfies the first resource utilization amount; wherein to report the utilization to the compute device comprises to report the utilization in response to a determination that the utilization does not satisfy the first resource utilization amount.",
"15. The one or more non-transitory machine-readable storage media of claim 14, to adjust the first resource utilization amount comprises to: receive an adjustment to the first resource utilization amount from the compute device; and apply the adjustment to the first resource utilization amount to determine the second resource utilization amount.",
"16. The one or more non-transitory machine-readable storage media of claim 14, wherein to receive the first workload comprises to receive a designation of a logic portion to execute the first workload.",
"17. The one or more non-transitory machine-readable storage media of claim 12, wherein to receive the first workload comprises to receive a bit stream indicative of the first workload to be accelerated.",
"18. The one or more non-transitory machine-readable storage media of claim 12, wherein to identify the first resource utilization amount comprises to receive resource utilization data indicative of the first resource utilization amount from an orchestrator server.",
"19. The one or more non-transitory machine-readable storage media of claim 12, wherein to identify the first resource utilization amount comprises to receive resource utilization data indicative of the first resource utilization amount from a processor of a first compute device that is assigned to execute a portion of the first workload.",
"20. The one or more non-transitory machine-readable storage media of claim 12, wherein to identify the first resource utilization amount comprises to receive a resource utilization amount indicative of an amount of memory to be used by the first logic portion, the memory to include dynamic random access memory.",
"21. The one or more non-transitory machine-readable storage media of claim 12, wherein to identify the first resource utilization amount comprises to receive a resource utilization amount indicative of an amount of data storage to be used by the first logic portion.",
"22. The one or more non-transitory machine-readable storage media of claim 12, wherein to identify the first resource utilization amount comprises to receive a resource utilization amount of an amount of network bandwidth to be used by the first logic portion.",
"23. The one or more non-transitory machine-readable storage media of claim 12, wherein to identify the first resource utilization amount comprises to receive an identifier of a class of service associated with an amount of a resource to be used by the first logic portion.",
"24. The one or more non-transitory machine-readable storage media of claim 12, wherein the plurality of instructions, when executed, further cause the accelerator device to: receive a second workload associated with a second application, the second workload to be executed by a second logic portion of the plurality of logic portions; identify a third resource utilization amount associated with the at least one shared resource to be used by the second logic portion to execute the second workload, limit, as a function of the third resource utilization amount, a utilization of the at least one shared resource by the second logic portion to not exceed the third resource utilization amount as the second logic portion executes the second workload, and adjust the third resource utilization amount to a fourth resource utilization amount as the second workload is executed by the second logic portion.",
"25. A method comprising: receiving, by an accelerator device, a first workload associated with a first application, the first workload to be executed by a first logic portion of a plurality of logic portions of a field programmable gate array (FPGA) of the accelerator device, the plurality of logic portions capable of separately executing a respective workload; identifying a first resource utilization amount associated with at least one shared resource of the accelerator device to be used by the first logic portion to execute the first workload; limiting, as a function of the first resource utilization amount, a utilization of the at least one shared resource by the first logic portion to not exceed the first resource utilization amount as the first logic portion executes the first workload; and adjusting, subsequent to the limiting of the utilization, the first resource utilization amount to a second resource utilization amount as the first workload is executed by the first logic portion.",
"26. The method of claim 25, further comprising: monitoring the utilization of the at least one shared resource by the first logic portion as the first workload is executed; and reporting the utilization to a computing device.",
"27. The method of claim 26, further comprising: determining whether the utilization of the at least one shared resource satisfies the first resource utilization amount; wherein reporting utilization to the computing device comprises to report the utilization in response to a determination that the utilization does not satisfy the first resource utilization amount.",
"28. The method of claim 25, further comprising: receiving a second workload associated with a second application, the second workload to be executed by a second logic portion of the plurality of logic portions; identifying a third resource utilization amount associated with the at least one shared resource to be used by the second logic portion to execute the second workload, limiting, as a function of the third resource utilization amount, a utilization of the at least one shared resource by the second logic portion to not exceed the third resource utilization amount as the second logic portion executes the second workload, and adjusting the third resource utilization amount to a fourth resource utilization amount as the second workload is executed by the second logic portion."
],
"description_excerpt": "Typical architectures for accelerator devices such as field programmable gate arrays (FPGAs), cryptography accelerators, graphics accelerators, and/or compression accelerators (referred to herein as “accelerators” or “accelerator resources”) capable of accelerating the execution of a set of operations in a workload (e.g., processes, applications, services, etc.) may allow static assignment of specified amounts of shared resources of the accelerator device (e.g., high bandwidth memory, data storage, etc.) among different portions of the logic (e.g., circuitry) of the accelerator device. Each logic portion may execute a separate set of operations to be accelerated, such as on behalf of different customers of a cloud data center. The resource needs of the logic portions may change as their workloads are executed, such that while a particular logic portion may be allocated 60% of the available high bandwidth memory, it only uses 30% of the high bandwidth memory during certain phases of the workload. During those phases, other logic portions of the accelerator device that might benefit from using more of the high bandwidth memory are prevented from doing so, as the allocations are statically defined. Changing the allocation of shared resources among the logic portions of the accelerator device typically involves stopping the execution of the workloads and reconfiguring the logic portions to use different amounts of the shared resources, and then resuming operation of the workloads.",
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],
"assignees": [
"Intel Corp"
],
"inventors": [
"Francesc Guim Bernat",
"Susanne M. Balle",
"Rahul Khanna",
"Sujoy Sen",
"Karthik Kumar"
],
"filing_date": "2021-04-20",
"publication_date": "2022-05-17",
"grant_date": "2022-05-17",
"priority_date": "2016-07-22",
"application_number": "US-202117235135-A",
"family_id": "60804962",
"cited_by_count": 0,
"citations": [
"US20120233488A1",
"US8990351B2",
"US8762916B1",
"US20150033134A1",
"US20170220499A1",
"US10461774B2",
"US10616668B2"
]
}
Record 1,167 of 8,000 in Patents full text (MLC-0201). Request the full dataset.