Memory controller and memory system having the same

{
  "publication_number": "US11061608B2",
  "country": "US",
  "kind": "B2",
  "title": "Memory controller and memory system having the same",
  "abstract": "A memory system includes a memory controller. The memory controller includes: a buffer memory configured to store read count values of memory blocks and address mapping information of the memory blocks; and a central processing unit configured to monitor the read count values, and determine whether a refresh operation of target blocks, among the memory blocks, is to be performed on all memory blocks including target blocks in a super block, in a unit of the super block or on the target memory blocks in the super block in a unit of a single block, based on the monitoring result.",
  "claims": [
    "1. A memory controller for controlling a storage device having a plurality of memory devices, the memory controller comprising: a buffer memory configured to store read count values of memory blocks included in the plurality of memory devices and address mapping information of the memory blocks; and a central processing unit configured to monitor the read count values, determine target blocks based on whether each of the read count values of the memory blocks is greater than a threshold value, and determine whether a refresh operation of the determined target blocks, among the memory blocks, is to be performed on all memory blocks including the target blocks in a super block in a unit of the super block, or on the target blocks in the super block in a unit of a single block, based on whether a number of the determined target blocks included in a super block is greater than a set number.",
    "2. The memory controller of claim 1, wherein the buffer memory includes: a read count table configured to store and update the read count value of each of the memory blocks on which a read operation is performed; a super block table configured to store addresses of the memory blocks included in the super blocks; a logical-to-physical (L2P) table configured to store a physical address mapped to a logical address; and a physical-to-logical (P2L) table configured to store the logical address mapped to the physical address.",
    "3. The memory controller of claim 1, wherein the central processing unit includes: a refresh monitor configured to monitor the read count values, and compare the number of target blocks with the set number, and output a count signal; a command generator configured to output a command for performing the refresh operation in response to the count signal; and an address management component configured to output an index for outputting an address from the buffer memory in response to the count signal.",
    "4. The memory controller of claim 3, wherein the refresh monitor includes: a read counter configured to count a number of read operations performed in the respective memory blocks in memory devices, and store the corresponding read count values in the buffer memory; and a count detector configured to calculate the number of target blocks to be refreshed by comparing each of the read count values with the threshold value, compare the number of the target blocks with the set number, and output a count signal.",
    "5. The memory controller of claim 4, wherein the threshold value and the set number depend on the memory devices.",
    "6. The memory controller of claim 4, wherein the read counter: sorts, as the target blocks, blocks of which the read count value is greater than the threshold value; and initializes the read count value of each of the target blocks on which the refresh operation has been completed.",
    "7. The memory controller of claim 6, wherein the read counter controls the buffer memory to initialize the read count values of the target blocks on which the refresh operation has been completed.",
    "8. The memory controller of claim 4, wherein the command generator: when it is determined that the number of the target blocks is greater than the set number according to the count signal, outputs a command for performing the refresh operation on the memory blocks in the unit of the super block; and when it is determined that the number of the target blocks is less than the set number according to the count signal, outputs a command for performing the refresh operation on the memory blocks in the unit of the single block.",
    "9. The memory controller of claim 4, wherein the address management component: when it is determined that the number of the target blocks is greater than the set number according to the count signal, outputs an index for performing the refresh operation on the memory blocks in the unit of the super block; and when it is determined that the number of the target blocks is less than the set number according to the count signal, outputs an index for performing the refresh operation on the memory blocks in the unit of the single block.",
    "10. The memory controller of claim 9, wherein the buffer memory outputs addresses of blocks on which the refresh operation is to be performed according to the index.",
    "11. The memory controller of claim 1, wherein, when the refresh operation is performed in the unit of the super block, the central processing unit controls memory devices including memory blocks in the super block to perform the refresh operation on all the memory blocks in the super block.",
    "12. The memory controller of claim 1, wherein, when the refresh operation is performed in units of the single blocks, the central processing unit controls memory devices including memory blocks on which the refresh operation is to be performed to perform the refresh operation on only the memory blocks.",
    "13. The memory controller of claim 1, wherein the central processing unit controls the buffer memory to initialize the read count value of the memory blocks of which refresh operation has been completed.",
    "14. A memory system comprising: a plurality of memory devices including a plurality of memory blocks; and a memory controller configured to: determine target blocks based on whether each of read count values of the plurality of memory blocks in the plurality of memory devices is greater than a threshold value, when a refresh operation is performed on target blocks, on which the refresh operation is to be performed, among the plurality of memory blocks, control the plurality of memory devices to perform the refresh operation on all memory blocks in a super block including the target blocks in a unit of the super block, or on an individual block basis in the super block in a unit of a single block, according to whether a number of target blocks in the super block is greater than a set number.",
    "15. The memory system of claim 14, wherein each of the memory blocks in each of the memory devices is in a user block or a reserved block.",
    "16. The memory system of claim 15, wherein the memory blocks on which the refresh operation is to be perform are blocks in the user block, and the memory blocks in the reserved block are used to temporarily store data of memory blocks included in the user block in the refresh operation.",
    "17. The memory system of claim 14, wherein the memory controller includes: a buffer memory configured to store the read count values of the memory blocks and address mapping information of the memory blocks; and a central processing unit configured to monitor the read count values, and determine whether the refresh operation of the target blocks, among the plurality of memory blocks, is to be performed in the unit of super block or in the unit of the single block, based on the monitoring result.",
    "18. The memory system of claim 17, wherein the buffer memory includes: a read count table configured to store and update the read count value of each of the memory blocks on which a read operation is performed; a super block table configured to store addresses of the memory blocks included in the super blocks; a logical-to-physical (L2P) table configured to store a physical address mapped to a logical address; and a physical-to-logical (P2L) table configured to store the logical address mapped to the physical address.",
    "19. The memory system of claim 17, wherein the central processing unit includes: a refresh monitor configured to monitor the read count values, and compare the number of target blocks with the set number, and output a count signal; a command generator configured to output a command for performing the refresh operation in response to the count signal; and an address management component configured to output an index for outputting an address from the buffer memory in response to the count signal.",
    "20. The memory system of claim 19, wherein the refresh monitor includes: a read counter configured to count a number of read operations performed in the respective memory blocks in the memory devices, and store the corresponding read count values in the buffer memory; and a count detector configured to calculate the number of target blocks to be refreshed by comparing each of the read count values with the threshold value, compare the number of target blocks with the set number, and output the count signal."
  ],
  "description_excerpt": "The present disclosure generally relates to a memory controller and a memory system having the same, and more particularly, to a memory controller capable of performing a refresh operation and a memory system having such a memory controller.\n\nA memory system may include a storage device and a memory controller.\n\nThe storage device may include a plurality of memory devices, which store data or output stored data. The memory devices may be volatile memory devices in which stored data is lost when the supply of power is interrupted, or nonvolatile memory devices in which stored data is retained even when the supply of power is interrupted.\n\nThe memory controller may control data communication between a host and the storage data.\n\nThe host may communicate with the storage device through the memory controller by using an interface protocol such as Peripheral Component Interconnect-Express (PCI-e or PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (DATA), or Serial Attached SCSI (SAS). Other interface protocols that may be used for communication between the host and the memory system include a Universal Serial Bus (USB), a Multi-Media Card (MMC), an Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).\n\nEmbodiments provide a memory controller capable of performing a refresh operation in units of super blocks or single blocks according to the number of refresh target blocks, and a memory system including the memory controller.",
  "cpc": [
    "G06F 3/0659",
    "G06F 12/0238",
    "G06F 12/0292",
    "G06F 12/1009",
    "G06F 13/1673",
    "G06F 2212/1032",
    "G06F 2212/1044",
    "G06F 2212/657",
    "G06F 2212/7201",
    "G06F 2212/7208",
    "G06F 3/0604",
    "G06F 3/064",
    "G06F 3/0653",
    "G06F 3/0656",
    "G06F 3/0673",
    "G11C 11/406",
    "G11C 11/40607",
    "G11C 11/40622",
    "G11C 11/408",
    "G11C 2029/0409",
    "G11C 7/1084"
  ],
  "ipc": [
    "G06F 12/1009",
    "G06F 3/06",
    "G11C 7/10"
  ],
  "assignees": [
    "SK Hynix Inc"
  ],
  "inventors": [
    "Young Guen CHOI",
    "Dong Ham YIM"
  ],
  "filing_date": "2018-11-21",
  "publication_date": "2021-07-13",
  "grant_date": "2021-07-13",
  "priority_date": "2018-04-23",
  "application_number": "US-201816198269-A",
  "family_id": "68237864",
  "cited_by_count": 4,
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}