Encapsulated electronic component and production method

{
  "publication_number": "US2006151203A1",
  "country": "US",
  "kind": "A1",
  "title": "Encapsulated electronic component and production method",
  "abstract": "The present invention relates to an encapsulated component that includes a carrier substrate and at least one chip positioned on the top of the carrier substrate and electrically connected to it by means of electrically conductive connections. The encapsulation of the chip is accomplished with a seal or dielectric layer. As a result of differing coefficients of expansion of the seal or dielectric layer and the electrically conductive connections, with changing temperatures stresses occur in the electrically conductive connections, which can lead to cracks, breaks and even to interruption of the electrically conductive connections. To mechanically relieve the electrically conductive connections of stresses from changing temperatures (in particular under extreme thermal loads), it is proposed that the carrier substrate be provided with a support element that encircles the chip, which serves to support the seal or dielectric layer, and/or that the material and the arrangement of the encapsulation be selected accordingly.",
  "claims": [
    "1. A component comprising: a chip having a top surface and having a bottom surface that includes electrically conductive structures; a carrier substrate having a top surface that includes connecting areas, the chip being mounted in a flip chip arrangement on the carrier substrate via electrically conductive connections between the electrically conductive structures and the connecting areas; a support element on the top surface of the carrier substrate, the support element surrounding, the carrier substrate but not touching, the carrier substrate; and a seal that surrounds the chip and the support element; wherein the support element supports the seal.",
    "2. The component in of claim 1, wherein the electrically conductive connections comprise bumps.",
    "3. The component of claim 1, wherein the seal comprises a dielectric layer and substantially covers the top surface of the chip.",
    "4. The component of claim 3, wherein the dielectric layer comprises one or more layers.",
    "5. A component comprising: a chip having a top surface and having a bottom surface that includes electrically conductive structures; a carrier substrate having a top surface that includes connecting areas, the chip being mounted in a flip chip arrangement on the carrier substrate via electrically conductive connections between the electrically conductive structures and the connecting areas; and a composite over the top surface of the chip, the composite comprising a dielectric layer and a metal layer, this composite forming a seal with the carrier substrate outside of an area that corresponds to the chip; wherein the chip has a thickness such that a force resulting from thermal expansion of an electrically conductive connection in a temperature range between −60° C. and 85° C. per one is a maximum of 2 Newtons.",
    "6. A component comprising: a chip having a top surface and having a bottom surface that includes electrically conductive structures; a carrier substrate having a top surface that includes connecting areas, the chip being mounted in a flip chip arrangement on the carrier substrate via electrically conductive connections between the electrically conductive structures and the connecting areas; and a composite over the top surface of the chip, the composite comprising a dielectric layer and a metal layer above the dielectric layer relative to the top surface of the chip, the composite forming a seal with the carrier substrate outside of an area that corresponds to the chip; wherein the dielectric layer has a modulus of elasticity of less than 1 Gpa, a thickness of less than 20 μm, or a coefficient of thermal expansion that is greater than α bump /2 and that is less than 2 α bump, where α bump is a coefficient of thermal expansion for at least one of the electrically conductive connections.",
    "7. A component comprising: a chip having a top surface and having a bottom surface that includes electrically conductive structures; a carrier substrate having a top surface that includes connecting areas, the chip being mounted in a flip chip arrangement on the carrier substrate via electrically conductive connections between the electrically conductive structures and the connecting areas; and a support element on the top surface of the carrier substrate, the support element comprising a shrink frame that substantially encloses the chip.",
    "8. The component in of claim 7, further comprising a metal layer that substantially covers the top surface of the chip; and wherein the shrink frame forms a seal with the carrier substrate.",
    "9. The component of claim 1, 5, 6, or 7, wherein the chip has side surfaces that are sloped so that a cross-section of the chip tapers toward the carrier substrate.",
    "10. The component of claim 1, 5, 6, or 7, wherein the chip has side surfaces that comprise at least one step.",
    "11. The component of claim 1, wherein the seal covers edge areas of the chip and the support element; and, wherein the seal does not cover the top surface of the chip.",
    "12. The component of claim 1, further comprising a metal layer (ME) above the seal relative to the top surface of the chip, the metal layer being on edge areas of the support element and/or on edge areas of the carrier substrate.",
    "13. The component of claim 3, wherein the dielectric layer completely covers the chip and the support element, the dielectric layer forming a seal with the carrier substrate only of in areas that do not correspond to the support element so that the chip and the support element are in a shared space that is formed between the dielectric layer and the top surface of the carrier substrate.",
    "14. The component of claim 3, wherein the dielectric layer completely covers the top surface of the chip and seals to the support element, with the support element comprising a hermetically tight material.",
    "15. The component of claim 3, further comprising a metal layer that substantially covers the dielectric layer.",
    "16. The component of claim 3, further comprising a filling compound on the dielectric layer.",
    "17. The component of claim 16, further comprising a metal layer that forms a seal with the support element outside of an area that corresponds to the chip, or that forms a seal with the carrier substrate outside of an area that corresponds to the support element.",
    "18. The component of claim 1 or 7, further comprising a contact metallization on side surfaces of the chip that face the carrier substrates; wherein the support element comprises a solder frame, the support element being soldered to a contact metallization of the chip.",
    "19. The component of claim 18, further comprising a metal layer above a top surface of the chip.",
    "20. The component of claim 1, wherein the seal comprises a dielectric material.",
    "21. The component of claim 20, wherein the seal comprises at least one of a plastic, an organic plastic, a laminate film, a glass solder and a resin.",
    "22. The component of claim 3, wherein the dielectric layer comprises at least one of a plastic, an organic plastic, a laminate film, a glass solder and a resin.",
    "23. The component of claim 1, wherein the support element comprises at least one of metal, a ceramic material and plastic.",
    "24. The component of claim 1, wherein the support element corresponds to a boundary of an indentation on the carrier substrate.",
    "25. The component of claim 1, wherein a height of the support element does not exceed a distance between the top surface of the carrier substrate and a bottom edge of the chip; and wherein an the inner edge of the support element is under the bottom edge of the chip.",
    "26. The component of claim 1, wherein a height of the support element corresponds to, or exceeds, a distance between the top surface of the carrier substrate and a bottom edge of the chip.",
    "27. The component of claim 1, 5, 6, or 7, wherein the carrier substrate comprises a low temperature cofired ceramic.",
    "28. The component of claim 1, 5, 6, or 7, further comprising surface-mounted-device-capable external contacts on a bottom surface of the carrier substrate.",
    "29. The component of claim 1, 5, 6, or 7, wherein the carrier substrate comprises at least two dielectric layers.",
    "30. The component of claim 1, 5, 6, or 7, wherein the chip contains comprises at least one resonator that works with acoustic surface waves or acoustic volume waves.",
    "31. The component of claim 1, 5, 6, or 7, further comprising similar or different chips that are attached to the carrier substrate and that are similarly encapsulated.",
    "32. A method for producing an encapsulated component using a chip having either (i) sloping side surfaces that taper, or (ii) stepped side surfaces, the method comprising: applying metallization to a top surface of a carrier substrate; applying a solder frame is produced on to the carrier substrate; placing the chip on the carrier substrate in a flip chip arrangement; and soldering contact metallization on side surfaces of the chip to the solder frame.",
    "33. The method of claim 32, further comprising applying insulating non-wettable structures to the chip between the contact metallization and electrically conductive structures associated with the chip.",
    "34. The method of claim 32, further comprising applying a metal layer to a top surface of the chip.",
    "35. A method for producing an encapsulated component using a chip having a surface with electrically conductive structures, and using a substrate having a top surface with connecting areas for making contact with the chip and a frame that is capable of shrinking, the method comprising: placing the chip on the carrier substrate; soldering the chip to the carrier substrate in a flip chip arrangement; shrinking the frame through heating so that the frame encloses the chip, and forming a metal layer over the top surface of the chip and the frame.",
    "36. The method of claim 35, wherein one side of the frame comprises a connection layer, the connection layer comprising a solderable layer or with an adhesive layer; and connecting the frame to the carrier substrate via the connection layer.",
    "37. A method for producing an encapsulation for an electrical component, the method comprising: attaching, to a carrier substrate, at least two chips having conductive structures, the at least two chips being attached to the carrier substrate in a flip chip arrangement via electrically conductive connections between connecting areas of the carrier substrate and the conductive structures; covering the at least two chips with a dielectric layer that seals to the carrier substrate so that each of the at least two chips is individually encapsulated and at least one space exists between the at least two chips; and adding a filling compound to the at least one space.",
    "38. The method as recited in of claim 37, further comprising: applying a metal layer to the dielectric layer, the metal layer forming a composite with the dielectric layer, and adding the filling compound to the composite.",
    "39. The method of claim 37, further comprising: separating the carrier substrate to produce individual components, wherein each of the individual components includes one of the at least two chips."
  ],
  "cpc": [
    "H03H 9/0557",
    "H03H 9/059",
    "H03H 9/1071",
    "H03H 9/1078",
    "H10D 62/117",
    "H10W 42/276",
    "H10W 70/655",
    "H10W 70/682",
    "H10W 70/685",
    "H10W 72/0198",
    "H10W 72/90",
    "H10W 72/9415",
    "H10W 72/952",
    "H10W 74/142",
    "H10W 74/15",
    "H10W 90/724",
    "H10W 90/734",
    "Y10T 29/49146"
  ],
  "assignees": [
    "KRUEGER HANS",
    "PORTMANN JURGEN",
    "NICOLAUS KARL",
    "FEIERTAG GREGOR",
    "STELZL ALOIS"
  ],
  "filing_date": "2003-06-23",
  "publication_date": "2006-07-13",
  "priority_date": "2002-08-22",
  "application_number": "US-52387505-A",
  "family_id": "31197251",
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}