Non-volatile semiconductor memory with bit line hierarchy

{
  "publication_number": "US2012243335A1",
  "country": "US",
  "kind": "A1",
  "title": "Non-volatile semiconductor memory with bit line hierarchy",
  "abstract": "Local bit lines (LBL) are respectively provided for a plurality of sectors, corresponding to each of the global bit lines (GBL). Sector select transistors connect a LBL to a GBLector select lines control the on/off state of the sector select transistors for the corresponding sectors. A plurality of word lines (WL) intersect the local bit lines. Memory cells are located at the intersections between the LBL and the WL. Each memory cell connects a source line with the corresponding LBL and includes an n-channel transistor that is turned on/off by the corresponding WL. A precharge voltage is applied to a charging line. Charging transistors connect the LBL to the charging line. A charging gate line controls the on/off state of the charging transistors.",
  "claims": [
    "1. A non-volatile semiconductor memory comprising: a plurality of global bit lines; a plurality of local bit lines provided for each of the global bit lines, each of the local bit lines defining a sector; a sector select transistor provided for each of the sectors, connecting the corresponding local bit line with the corresponding global bit line; sector select lines respectively provided for the corresponding sectors, controlling on/off state of sector select transistors; a plurality of word lines intersecting the local bit lines; a source line; memory cells located at intersections between the local bit lines and the word lines, each of the memory cells connecting the source line with the corresponding local bit line, and containing an n-channel memory transistor that is turned on/off by the corresponding word line; a charging line to which a precharge voltage is applied; charging transistors respectively provided for the corresponding local bit lines and connecting the corresponding local bit lines with the charging line; charging gate lines controlling on/off state of the charging transistors; and control circuit controlling electric signals applied to the global bit lines, the sector select lines, the word lines, the source line, the charging line, and the charging gate lines. 2. A non-volatile semiconductor memory as defined in claim 1, wherein the transistors constituting a circuit that controls the electric signals applied to the global bit lines have a gate insulation film which is thinner than a gate insulation film of the transistors constituting a circuit that controls the electric signals applied to the word lines. 3. A non-volatile semiconductor memory as claimed in claim 1, wherein the transistors constituting a circuit that controls the electric signals applied to the sector select lines have a gate insulation film which is thinner than a gate insulation film of the transistors constituting a circuit that controls the electric signals applied to the word lines. 4. A non-volatile semiconductor memory as defined in claim 1, wherein the control circuit, during the write process, applies data signals to the plurality of global bit lines, applies the precharge voltage to the local bit lines by turning off the sector select transistors and turning on the charging transistors, and causes an electric current to flow in the memory cell where datum is to be written, by applying word line select signal to the word line to which the memory cell where datum is to be written is connected, turning on the sector select transistor connected to the local bit line that corresponds to the memory cell where datum is to be written, and discharging the local bit line, so that datum is written. 5. A non-volatile semiconductor memory as defined in claim 4, wherein the control circuit applies a precharge voltage to the charging line after turning on the charging transistor, before turning on the sector select transistor. 6. A non-volatile semiconductor memory as defined in claim 5, wherein the source voltage applied to the source line is equal to the precharge voltage applied to the charging line. 7. A non-volatile semiconductor memory comprising: a plurality of global bit lines; a plurality of local bit lines provided for each of the global bit lines, each of the local bit lines defining a sector; a sector select transistor provided for each of the sectors, connecting the corresponding local bit line with the corresponding global bit line; sector select lines respectively provided for the corresponding sectors, controlling on/off state of the sector select transistors; a plurality of row select lines intersecting the local bit lines; a source line; memory cells located at intersections between the local bit lines and the row select lines, each of the memory cells connecting the source line with the corresponding local bit line, and being controlled its conductivity by the corresponding row select line; a charging line to which a precharge voltage is applied; charging transistors respectively provided for the corresponding local bit lines and connecting the corresponding local bit lines with the charging line; charging gate lines controlling on/off state of the charging transistors; and control circuit controlling electric signals applied to the global bit lines, the sector select lines, the word lines, the source line, the charging line, and the charging gate lines; wherein the control circuit, during the write process, applies the precharge voltage to the charging line, to turn on the charging transistors, and apply the precharge voltage to the local bit line, followed by turning on the sector select transistor connected to the local bit line corresponding to the memory cell where datum is to be written to discharge the local bit line. 8. A non-volatile semiconductor memory as defined in claim 7, wherein the transistors constituting a circuit that controls the electric signals applied to the global bit lines have a gate insulation film which is thinner than a gate insulation film of the transistors constituting a circuit that controls the electric signals applied to the row select lines. 9. A non-volatile semiconductor memory as claimed in claim 7, wherein the transistors constituting a circuit that controls the electric signals applied to the sector select lines have a gate insulation film which is thinner than a gate insulation film of the transistors constituting a circuit that controls the electric signals applied to the row select lines. 10. A non-volatile semiconductor memory as defined in claim 7, wherein each of the memory cells comprises a select transistor and a memory transistor, the memory transistor has a drain connected to the corresponding local bit line through the select transistor, the select transistor being turned on/off by the corresponding row select line, and the memory transistor has a source connected to the source line."
  ],
  "description_excerpt": "The embodiments of the invention relate to non-volatile semiconductor memories comprising a hierarchical bit line structure in which a plurality of local bit lines are connected to each of global bit lines.\n\nTo achieve a larger memory capacity in a smaller chip area, some NOR type non-volatile semiconductor memory devices have a hierarchical bit line structure in which a plurality of local bit lines are connected to each of global bit lines. Described below is the working mechanism of a typical conventional n-channel floating gate type flash memory with a bit line hierarchy.\n\nTo write data, 5V, 0V, and 9V are applied to the local bit line (drain), source line, and word line (gate) for the selected cell. Electrons accelerated between the source and the drain are injected into the floating gate to cause a negative voltage, thereby decreasing the effective gate voltage applied to the gate (control gate). This increases the required gate voltage for inducing an inversion layer at the channel surface, leading to an increased threshold voltage of the memory transistor.\n\nTo erase data, the local bit line and the source line are brought into a floating state, and 9V and −9V are applied to the p-type well containing the memory transistor and the word line (gate), respectively. The negative voltage is removed as the electrons stored in the floating gate are extracted into the substrate. The threshold voltage of the memory transistor decreases, and becomes lower than that in the state when electrons were stored.",
  "cpc": [
    "G11C 16/06",
    "G11C 16/0416",
    "G11C 16/0483",
    "G11C 16/349"
  ],
  "ipc": [
    "G11C 16/06",
    "G11C 16/04",
    "G11C 16/34"
  ],
  "assignees": [
    "Fujitsu Semiconductor Ltd"
  ],
  "inventors": [
    "Satoshi Torii"
  ],
  "filing_date": "2012-03-21",
  "publication_date": "2012-09-27",
  "priority_date": "2011-03-22",
  "application_number": "US-201213426463-A",
  "family_id": "46877249",
  "cited_by_count": 5,
  "citations": [
    "US20020167853A1",
    "US6621744B2",
    "US20120147686A1"
  ]
}