Method for PUF generation using variations in transistor threshold voltage and subthreshold leakage current

{
  "publication_number": "US11043404B2",
  "country": "US",
  "kind": "B2",
  "title": "Method for PUF generation using variations in transistor threshold voltage and subthreshold leakage current",
  "abstract": "Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator comprising: a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a first MOS transistor and a second MOS transistor, wherein terminal S of the first MOS transistor is connected to terminal D of the second MOS transistor at a dynamic node, terminal D of the first MOS transistor is coupled to a first bus and terminal G of the first NMOS transistor is coupled to a second bus, and terminals S and G of the second NMOS transistor are coupled to ground; a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively; a population count circuit coupled to the plurality of DFF circuits; and an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of DFF circuits.",
  "claims": [
    "1. A physical unclonable function (PUF) generator comprising: a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a first metal oxide semiconductor (MOS) transistor and a second MOS transistor, wherein a source of the first MOS transistor is connected to a drain of the second MOS transistor at a dynamic node, a drain of the first MOS transistor is coupled to a first bus and a gate of the first MOS transistor is coupled to a second bus, and a source and a gate of the second MOS transistor are coupled to ground; a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively, wherein the plurality of DFF circuits each is configured to monitoring a voltage level on the dynamic node on each of the plurality of PUF cells; a population count circuit coupled to the plurality of DFF circuits, wherein the population count circuit is configured to determine a first number of PUF cells having flipped logical states from a first logical state to a second logical state; and an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of DFF circuits, wherein the evaluation logic circuit is configured to compare the first number with half of a total number of PUF cells, wherein a PUF signature is generated when the number of PUF cells that are at the second logical state are equal to or higher than half of the total number of PUF cells in the PUF generator.",
    "2. The PUF generator of claim 1, wherein the first and second MOS transistors each comprise an n-type MOS (NMOS) transistor.",
    "3. The PUF generator of claim 1, wherein the second bus is coupled to a high voltage level at a first time so as to charge the dynamic node to a first voltage that is different from a voltage on the first bus.",
    "4. The PUF generator of claim 3, wherein the second bus is coupled to a low voltage level at a second time so as to discharge the dynamic node to a second voltage at a third time through the second MOS transistor.",
    "5. The PUF generator of claim 4, wherein the plurality of DFF circuits is configured to determine when the dynamic nodes of respective PUF cells flip from the first logical state to the second logical state.",
    "6. The PUF generator of claim 4, wherein the plurality of DFF circuits configures a plurality of third voltages.",
    "7. The PUF generator of claim 6, wherein the flip from the first logical state to the second logical state is determined when the second voltage at the third time on the dynamic node of the PUF cell becomes lower than the third voltage of the corresponding DFF circuit.",
    "8. The PUF generator of claim 1, wherein the population count circuit is configured to detect a number of PUF cells that are at the second logical state.",
    "9. The PUF generator of claim 1, wherein the evaluation logic circuit is further configured to compare the number of PUF cells that are at the second logical state to a total number of PUF cells in the PUF generator in order to generate a PUF signature.",
    "10. The PUF generator of claim 1, wherein the PUF signature is a multi-bit binary sequence comprising a combination of logical states of each of the plurality of PUF cells in the PUF generator.",
    "11. A method to configure a physical unclonable function (PUF) generator for generating a PUF signature, the method comprising: coupling a plurality of PUF cells to a plurality of dynamic flip-flop (DFF) circuits, and to a population counter and further to an evaluation logical circuit, wherein each of the plurality of PUF cells comprises a first metal oxide semiconductor (MOS) transistor and a second MOS transistor; charging a plurality of dynamic nodes in the plurality of PUF cells to a plurality of first voltages through each of the plurality of first MOS transistors; discharging the plurality of dynamic nodes to a plurality of second voltages through each of the plurality of second MOS transistors; monitoring each of the plurality of second voltages using corresponding DFF circuits; flipping logical states of the plurality of PUF cells from a first logical state to a second logical state when the second voltage becomes smaller than a third voltage; and generating a PUF signature when a number of PUF cells having flipped logical states are more than half of a total number of PUF cells.",
    "12. The method of claim 11, wherein the first MOS transistor is configured having a source terminal coupled to a drain terminal of the second MOS transistor at the dynamic node, a drain coupled to a first bus, and a gate terminal coupled to a second bus.",
    "13. The method of claim 11, wherein the second MOS transistor is configured having a source and a gate terminal coupled to ground.",
    "14. The method of claim 11, wherein the first and second MOS transistors each comprise a NMOS transistor.",
    "15. The method of claim 11, wherein the first voltages on the dynamic nodes of corresponding PUF cells is determined by threshold voltages of the first MOS transistors of corresponding PUF cells.",
    "16. The method of claim 11, wherein the time required for the dynamic nodes to discharge to the second voltages are determined by current leakage through the second MOS transistors of corresponding PUF cells.",
    "17. The method of claim 11, wherein the third voltage is determined by the corresponding DFF circuits.",
    "18. A physical unclonable function (PUF) generator comprising: a plurality of PUF cells; a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively, wherein the plurality of DFF circuits each is configured to monitoring a voltage level on a dynamic node on each of the plurality of PUF cells; a population count circuit coupled to the plurality of DFF circuits, wherein the population count circuit is configured to determine a first number of PUF cells having flipped logical states from a first logical state to a second logical state; and an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of DFF circuits, wherein the evaluation logic circuit is configured to compare the first number with half of a total number of PUF cells, wherein a PUF signature is generated when the number of PUF cells that are at the second logical state are equal to or higher than half of the total number of PUF cells in the PUF generator.",
    "19. The PUF generator of claim 18, wherein the population count circuit is configured to detect a number of PUF cells that are at the second logical state.",
    "20. The PUF generator of claim 18, wherein the evaluation logic circuit is further configured to compare the number of PUF cells that are at the second logical state to a total number of PUF cells in the PUF generator in order to generate a PUF signature."
  ],
  "description_excerpt": "With the increasing use of integrated circuits in electronic devices that provide different types of information for a variety of different applications, there has been an increasing need to adequately protect sensitive and/or critical information that may be stored within an electronic device to limit access to such information to only other devices that have permission to access. Some examples of such applications include the authentication of devices, protection of confidential information within a device, and securing a communication between two or more devices. It has become widely recognized that random number generators are fundamentally important in the computer age. A high quality random number generator to generate true random numbers is desirable for cryptographic applications. For example, true random numbers are used as an encryption key for encrypting information and messages.\n\nA physically unclonable function (PUF) generator is a physical structure generally within an integrated circuit that provides a number of corresponding outputs (e.g., responses) in response to inputs (e.g., challenges/requests) to the PUF generator. There are many different implementation approaches including delay-chain-based PUF generators and memory-based PUF generators. A memory-based PUF generator translates the variations in an array of memory devices, typically either SRAM (static random-access memory) or DRAM (dynamic random-access memory) devices, into a binary sequence.",
  "cpc": [
    "H10P 72/50",
    "B25J 11/0095",
    "B25J 9/1664",
    "B25J 9/1692",
    "G09C 1/00",
    "G11C 2029/4402",
    "G11C 2029/5002",
    "G11C 7/24",
    "G11C 8/12",
    "H01L 21/67265",
    "H01L 21/67386",
    "H01L 21/68",
    "H01L 21/681",
    "H04L 9/0866",
    "H04L 9/3247",
    "H04L 9/3278",
    "H10P 72/0608",
    "H10P 72/1922",
    "H10P 72/53",
    "Y04S 40/20"
  ],
  "ipc": [
    "B25J 11/00",
    "B25J 9/16",
    "H01L 21/67",
    "H01L 21/673",
    "H01L 21/68",
    "H04L 29/06"
  ],
  "assignees": [
    "Taiwan Semiconductor Manufacturing Co TSMC Ltd"
  ],
  "inventors": [
    "Shih-Lien Linus Lu",
    "Cormac Michael O'CONNELL"
  ],
  "filing_date": "2018-04-27",
  "publication_date": "2021-06-22",
  "grant_date": "2021-06-22",
  "priority_date": "2017-11-14",
  "application_number": "US-201815965429-A",
  "family_id": "67347864",
  "cited_by_count": 2,
  "citations": [
    "US20140218067A1",
    "US20160285639A1",
    "US9966954B1"
  ]
}