Circuit and method for reducing parasitic bipolar effects during electrostatic discharges

{
  "publication_number": "US6284616B1",
  "country": "US",
  "kind": "B1",
  "title": "Circuit and method for reducing parasitic bipolar effects during electrostatic discharges",
  "abstract": "A semiconductor device including a current source having a first node coupled to a terminal, and a second node for extracting a current in response to an electrostatic discharge (ESD) on the terminal. The semiconductor device further including a transistor having a control electrode, a first current electrode coupled to the terminal, and a second current electrode coupled to the second node of the current source, and including a resistive element coupled to a first voltage reference node and the second node of the current source. The transistor of the semiconductor device is biased by detecting a negative voltage event (such as an ESD) at a first current electrode of the transistor and biasing a second current electrode of the transistor in response to detecting the negative voltage event, wherein the biasing of the second current electrode is for preventing a forward biasing of an p-n junction associated with the transistor.",
  "claims": [
    "1. A semiconductor device comprising: a terminal; a current source having a first node coupled to the terminal, and a second node for extracting a current in response to an electrostatic discharge (ESD) on the terminal; a first resistive element having a first node coupled to a first voltage reference node and a second node coupled to the second node of the current source; and a first transistor having a control electrode, a first current electrode coupled to the terminal, and a second current electrode coupled to the second node of the current source.",
    "2. The semiconductor device of claim 1, wherein the first transistor is a P-channel transistor.",
    "3. The semiconductor device of claim 2, wherein the first current electrode of the first transistor is a drain electrode, and the second current electrode is a source electrode.",
    "4. The semiconductor device of claim 1, wherein the current source further comprises a second transistor having a control gate, a first current electrode coupled to the first node of the current source, and a second current electrode coupled to the second node of the current source.",
    "5. The semiconductor device of claim 4, wherein the control gate of the second transistor is coupled to a second voltage reference node.",
    "6. The semiconductor device of claim 4, wherein the second transistor is a N-channel transistor.",
    "7. The semiconductor device of claim 4, wherein the current source further comprises a feedback circuit including a third transistor having a control electrode coupled to the first node of the current source, a first current electrode coupled to the first voltage reference node, and a second current electrode coupled to the control electrode of the second transistor.",
    "8. The semiconductor device of claim 7, further comprising: a fourth transistor having a control electrode, a first current electrode coupled to the terminal, and a second current electrode coupled to the control electrode of the third transistor; and a second resistive element having a first node coupled to the control electrode of the third transistor, and a second node coupled to the first voltage reference node."
  ],
  "description_excerpt": "The present invention generally relates to circuits, and more particularly, to a circuit and method for reducing parasitic bipolar effects during electrostatic discharges.\n\nAn integrated circuit or semiconductor device can be damaged when subjected to a voltage that is higher than the design voltage of the integrated circuit. Electrostatic discharge (“ESD”), originating from such sources as a mechanical chip carrier, a plastic chip storage device, or even a human being can generate a voltage that is many times greater than the design voltage of the integrated circuit. For example, the typical human body can supply an electrostatic discharge in excess of 4 kilovolts. For integrated circuits that operate at voltages of less than, for example, 5 volts, an electrostatic discharge of such proportions can be devastating.\n\nIn order to protect the internal circuitry from electrical overstress (EOS), or ESD, events, protection circuits are utilized, generally between the internal circuitry and the input/output (“I/O”) pins of the integrated circuit. One mechanism that can cause circuit failures during ESD events is a phenomenon known as “bipolar snapback”.\n\nA better understanding of the present invention can be obtained when the following detailed description of a preferred embodiment is considered in conjunction with the following drawings, in which:\n\nFIG. 1 illustrates, in partial schematic diagram form and partial cross-sectional view, a P-channel MOS transistor and an inherent parasitic bipolar transistor.",
  "cpc": [
    "H10D 89/815",
    "H10D 84/00",
    "H10D 89/601"
  ],
  "ipc": [
    "H10D 84/00",
    "H10D 84/03"
  ],
  "assignees": [
    "Motorola Inc"
  ],
  "inventors": [
    "Jeremy C. Smith"
  ],
  "filing_date": "2000-04-27",
  "publication_date": "2001-09-04",
  "grant_date": "2001-09-04",
  "priority_date": "1998-11-30",
  "application_number": "US-56050100-A",
  "family_id": "22745641",
  "cited_by_count": 23,
  "citations": [
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}