Patent · US9349859B1 · B1 · US

Top metal pads as local interconnectors of vertical transistors

(11) Publication number

US9349859B1

(21) Application number

14/608,958

(22) Filing date

2015-01-29

(30) Priority date

2015-01-29

(43) Publication date

2016-05-24

(45) Date of grant

2016-05-24

(51) IPC

H01L 21/8238; H01L 27/092; H01L 29/66; H01L 29/78; H01L 29/786; H10W 20/20

(52) CPC

H10D Inorganic electric semiconductor devices: 30/6713, 30/025, 30/63, 30/6715, 30/6728, 30/6735, 30/6741, 30/675, 30/6757, 62/116, 62/122, 84/0121, 84/0128, 84/013, 84/0149, 84/0151, 84/016, 84/0167, 84/017, 84/0186, 84/0188, 84/0195, 84/038, 84/83, 84/85, 86/021, 86/441, 86/60
H01L Semiconductor devices; electric solid state devices not otherwise provided for: 21/823871, 21/823885, 23/535, 27/092, 29/7827, 29/78642
H10W Generic packages, interconnections, connectors or other constructional details of devices covered by class H10: 20/054, 20/0698, 20/20

(73) Assignee

Taiwan Semiconductor Manufacturing Co TSMC Ltd

(72) Inventors

Wai-Yi Lien; Yi-Hsun CHIU; Jia-Chuan You; Yu-Xuan Huang; Chih-Hao Wang

(54) Title

Top metal pads as local interconnectors of vertical transistors

(57) Abstract

An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first semiconductor channel, a first top source/drain region over the first semiconductor channel, and a first top source/drain pad overlapping the first top source/drain region. The second vertical transistor includes a second semiconductor channel, a second top source/drain region over the second semiconductor channel, and a second top source/drain pad overlapping the second top source/drain region. A local interconnector interconnects the first top source/drain pad and the second top source/drain pad. The first top source/drain pad, the second top source/drain pad, and the local interconnector are portions of a continuous region, with no distinguishable interfaces between the first top source/drain pad, the second top source/drain pad, and the local interconnector.

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Claims (20)

An integrated circuit structure comprising: a first vertical transistor comprising: a first semiconductor channel; a first top source/drain region over the first semiconductor channel; and a first top source/drain pad overlapping the first top source/drain region; a second vertical transistor comprising: a second semiconductor channel; a second top source/drain region over the second semiconductor channel; and a second top source/drain pad overlapping the second top source/drain region; and a local interconnector interconnecting the first top source/drain pad and the second top source/drain pad, wherein the first top source/drain pad, the second top source/drain pad, and the local interconnector are portions of a continuous region, with no distinguishable interfaces between the first top source/drain pad, the second top source/drain pad, and the local interconnector.
The integrated circuit structure of claim 1, wherein each of the local interconnector, the first top source/drain pad, and the second top source/drain pad comprises a conductive barrier layer and a top metal layer over the conductive barrier layer.
The integrated circuit structure of claim 2 further comprising a metal silicide layer underlying and contacting each of the local interconnector, the first top source/drain pad, and the second top source/drain pad.
The integrated circuit structure of claim 1, wherein the first vertical transistor and the second vertical transistor are of opposite conductivity types.
The integrated circuit structure of claim 1, wherein the first vertical transistor and the second vertical transistor are of a same conductivity type.
The integrated circuit structure of claim 1, wherein the first top source/drain pad and the second top source/drain pad are wider than the local interconnector.
The integrated circuit structure of claim 1 further comprising: a first gate dielectric encircling the first semiconductor channel; a first gate electrode encircling the first gate dielectric; a second gate dielectric encircling the second semiconductor channel; and a second gate electrode encircling the second gate dielectric.
An integrated circuit structure comprising: a first vertical transistor comprising: a first semiconductor channel; a first top source/drain region over the first semiconductor channel; a first gate dielectric encircling the first semiconductor channel; and a first gate electrode encircling the first gate dielectric; a second vertical transistor comprising: a second semiconductor channel; a second top source/drain region over the second semiconductor channel; a second gate dielectric encircling the second semiconductor channel; and a second gate electrode encircling the second gate dielectric; a dielectric region between and separating the first gate electrode and the second gate electrode from each other; and a conductive feature comprising: a first portion having a first bottom surface contacting a top surface of the first top source/drain region; a second portion having a second bottom surface contacting a top surface of the second top source/drain region; and a third portion having a third bottom surface contacting a top surface of the dielectric region, wherein the third portion interconnects the first portion and the second portion.
The integrated circuit structure of claim 8, wherein the conductive feature comprises a silicide layer, with the first bottom surface, the second bottom surface, and the third bottom surface being bottom surfaces of the silicide layer.
The integrated circuit structure of claim 9, wherein the conductive feature further comprises a conductive barrier layer over and electrically connected to the silicide layer, with the conductive barrier layer and the silicide layer being co-terminus.
The integrated circuit structure of claim 9, wherein the conductive feature further comprises a top metal layer over and electrically connected to the silicide layer, with the top metal layer and the silicide layer being co-terminus.
The integrated circuit structure of claim 8, wherein the first vertical transistor and the second vertical transistor are of opposite conductivity types.
The integrated circuit structure of claim 8, wherein the first vertical transistor and the second vertical transistor are of a same conductivity type.
The integrated circuit structure of claim 8, wherein the conductive feature overlaps an entirety of the first semiconductor channel and an entirety of the second semiconductor channel.
A method comprising: forming a first vertical transistor comprising: a first semiconductor channel; and a first top source/drain region over the first semiconductor channel; forming a second vertical transistor comprising: a second semiconductor channel; and a second top source/drain region over the second semiconductor channel; forming a conductive layer over the first vertical transistor and the second vertical transistor and a region between the first vertical transistor and the second vertical transistor; and patterning the conductive layer, wherein remaining portions of the conductive layer comprise: a first portion having a first bottom surface contacting a top surface of the first top source/drain region; a second portion having a second bottom surface contacting a top surface of the second top source/drain region; and a third portion interconnecting the first portion and the second portion.
The method of claim 15 further comprising: forming a dielectric region between and separating the first vertical transistor and the second vertical transistor from each other, wherein the third portion of the remaining portions of the conductive layer has a bottom surface contacting the dielectric region.
The method of claim 15, wherein the forming the conductive layer comprises: blanket forming a conductive barrier layer; and blanket forming a top metal layer over the conductive barrier layer, wherein the conductive barrier layer and the top metal layer are both patterned in the patterning.
The method of claim 17, wherein the forming the conductive layer further comprises: before the blanket forming the conductive barrier layer, forming a silicide layer over the first vertical transistor and the second vertical transistor.
The method of claim 15, wherein the first vertical transistor and the second vertical transistor are of opposite conductivity types.
The method of claim 15, wherein the first vertical transistor and the second vertical transistor are of a same conductivity type.

Description

Transistors are key components of modern integrated circuits. To satisfy the requirements of increasingly faster switching speed, the drive currents of transistors need to be increasingly higher. At the same time, the gate lengths of transistors are constantly being scaled down. Scaling down the gate lengths leads to undesirable effects known as “short-channel effects,” with which the control of current flow by the gates is compromised. Among the short-channel effects are the drain-induced barrier lowering (DIBL) and the degradation of sub-threshold slope, both of which result in the degradation in the performance of transistors.

The use of multi-gate transistor architecture may help the relief of short-channel effects by improving electrostatic control of the gate on the channel. Fin field-effect transistors (FinFET) were thus developed. To further increase the control of the channels, and to reduce the short-channel effects, transistors having vertical gate-all-around structures were also developed, wherein the respective transistors are also referred to as Vertical Gate All Around (VGAA) transistors. In a VGAA transistor, a gate dielectric and a gate electrode fully encircle a channel region. This configuration delivers a good control of the channel, and the short-channel effects are reduced.

The connection to the source and drain regions of the VGAA transistors is through contact plugs and metal lines. Contact plugs are formed to electrically connect to the top source/drain regions, the bottom source/drain regions, and the gates of the VGAA transistors. Metal lines are used to interconnect the contact plugs.

Citations (25)

US20040113207A1
US20070010078A1
US7667271B2
US20100270611A1
US20110062515A1
US20110068407A1
US8362575B2
US8610240B2
US8497528B2
US8729627B2
US8796759B2
US8440517B2
US8367498B2
US20130011983A1
US8841701B2
US8723272B2
US8828823B2
US8847293B2
US8836016B2
US8785285B2
US8680576B2
US8729634B2
US8809139B2
US8853025B2
US20140252412A1

Record as JSON

{
  "publication_number": "US9349859B1",
  "country": "US",
  "kind": "B1",
  "title": "Top metal pads as local interconnectors of vertical transistors",
  "abstract": "An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first semiconductor channel, a first top source/drain region over the first semiconductor channel, and a first top source/drain pad overlapping the first top source/drain region. The second vertical transistor includes a second semiconductor channel, a second top source/drain region over the second semiconductor channel, and a second top source/drain pad overlapping the second top source/drain region. A local interconnector interconnects the first top source/drain pad and the second top source/drain pad. The first top source/drain pad, the second top source/drain pad, and the local interconnector are portions of a continuous region, with no distinguishable interfaces between the first top source/drain pad, the second top source/drain pad, and the local interconnector.",
  "claims": [
    "1. An integrated circuit structure comprising: a first vertical transistor comprising: a first semiconductor channel; a first top source/drain region over the first semiconductor channel; and a first top source/drain pad overlapping the first top source/drain region; a second vertical transistor comprising: a second semiconductor channel; a second top source/drain region over the second semiconductor channel; and a second top source/drain pad overlapping the second top source/drain region; and a local interconnector interconnecting the first top source/drain pad and the second top source/drain pad, wherein the first top source/drain pad, the second top source/drain pad, and the local interconnector are portions of a continuous region, with no distinguishable interfaces between the first top source/drain pad, the second top source/drain pad, and the local interconnector.",
    "2. The integrated circuit structure of claim 1, wherein each of the local interconnector, the first top source/drain pad, and the second top source/drain pad comprises a conductive barrier layer and a top metal layer over the conductive barrier layer.",
    "3. The integrated circuit structure of claim 2 further comprising a metal silicide layer underlying and contacting each of the local interconnector, the first top source/drain pad, and the second top source/drain pad.",
    "4. The integrated circuit structure of claim 1, wherein the first vertical transistor and the second vertical transistor are of opposite conductivity types.",
    "5. The integrated circuit structure of claim 1, wherein the first vertical transistor and the second vertical transistor are of a same conductivity type.",
    "6. The integrated circuit structure of claim 1, wherein the first top source/drain pad and the second top source/drain pad are wider than the local interconnector.",
    "7. The integrated circuit structure of claim 1 further comprising: a first gate dielectric encircling the first semiconductor channel; a first gate electrode encircling the first gate dielectric; a second gate dielectric encircling the second semiconductor channel; and a second gate electrode encircling the second gate dielectric.",
    "8. An integrated circuit structure comprising: a first vertical transistor comprising: a first semiconductor channel; a first top source/drain region over the first semiconductor channel; a first gate dielectric encircling the first semiconductor channel; and a first gate electrode encircling the first gate dielectric; a second vertical transistor comprising: a second semiconductor channel; a second top source/drain region over the second semiconductor channel; a second gate dielectric encircling the second semiconductor channel; and a second gate electrode encircling the second gate dielectric; a dielectric region between and separating the first gate electrode and the second gate electrode from each other; and a conductive feature comprising: a first portion having a first bottom surface contacting a top surface of the first top source/drain region; a second portion having a second bottom surface contacting a top surface of the second top source/drain region; and a third portion having a third bottom surface contacting a top surface of the dielectric region, wherein the third portion interconnects the first portion and the second portion.",
    "9. The integrated circuit structure of claim 8, wherein the conductive feature comprises a silicide layer, with the first bottom surface, the second bottom surface, and the third bottom surface being bottom surfaces of the silicide layer.",
    "10. The integrated circuit structure of claim 9, wherein the conductive feature further comprises a conductive barrier layer over and electrically connected to the silicide layer, with the conductive barrier layer and the silicide layer being co-terminus.",
    "11. The integrated circuit structure of claim 9, wherein the conductive feature further comprises a top metal layer over and electrically connected to the silicide layer, with the top metal layer and the silicide layer being co-terminus.",
    "12. The integrated circuit structure of claim 8, wherein the first vertical transistor and the second vertical transistor are of opposite conductivity types.",
    "13. The integrated circuit structure of claim 8, wherein the first vertical transistor and the second vertical transistor are of a same conductivity type.",
    "14. The integrated circuit structure of claim 8, wherein the conductive feature overlaps an entirety of the first semiconductor channel and an entirety of the second semiconductor channel.",
    "15. A method comprising: forming a first vertical transistor comprising: a first semiconductor channel; and a first top source/drain region over the first semiconductor channel; forming a second vertical transistor comprising: a second semiconductor channel; and a second top source/drain region over the second semiconductor channel; forming a conductive layer over the first vertical transistor and the second vertical transistor and a region between the first vertical transistor and the second vertical transistor; and patterning the conductive layer, wherein remaining portions of the conductive layer comprise: a first portion having a first bottom surface contacting a top surface of the first top source/drain region; a second portion having a second bottom surface contacting a top surface of the second top source/drain region; and a third portion interconnecting the first portion and the second portion.",
    "16. The method of claim 15 further comprising: forming a dielectric region between and separating the first vertical transistor and the second vertical transistor from each other, wherein the third portion of the remaining portions of the conductive layer has a bottom surface contacting the dielectric region.",
    "17. The method of claim 15, wherein the forming the conductive layer comprises: blanket forming a conductive barrier layer; and blanket forming a top metal layer over the conductive barrier layer, wherein the conductive barrier layer and the top metal layer are both patterned in the patterning.",
    "18. The method of claim 17, wherein the forming the conductive layer further comprises: before the blanket forming the conductive barrier layer, forming a silicide layer over the first vertical transistor and the second vertical transistor.",
    "19. The method of claim 15, wherein the first vertical transistor and the second vertical transistor are of opposite conductivity types.",
    "20. The method of claim 15, wherein the first vertical transistor and the second vertical transistor are of a same conductivity type."
  ],
  "description_excerpt": "Transistors are key components of modern integrated circuits. To satisfy the requirements of increasingly faster switching speed, the drive currents of transistors need to be increasingly higher. At the same time, the gate lengths of transistors are constantly being scaled down. Scaling down the gate lengths leads to undesirable effects known as “short-channel effects,” with which the control of current flow by the gates is compromised. Among the short-channel effects are the drain-induced barrier lowering (DIBL) and the degradation of sub-threshold slope, both of which result in the degradation in the performance of transistors.\n\nThe use of multi-gate transistor architecture may help the relief of short-channel effects by improving electrostatic control of the gate on the channel. Fin field-effect transistors (FinFET) were thus developed. To further increase the control of the channels, and to reduce the short-channel effects, transistors having vertical gate-all-around structures were also developed, wherein the respective transistors are also referred to as Vertical Gate All Around (VGAA) transistors. In a VGAA transistor, a gate dielectric and a gate electrode fully encircle a channel region. This configuration delivers a good control of the channel, and the short-channel effects are reduced.\n\nThe connection to the source and drain regions of the VGAA transistors is through contact plugs and metal lines. Contact plugs are formed to electrically connect to the top source/drain regions, the bottom source/drain regions, and the gates of the VGAA transistors. Metal lines are used to interconnect the contact plugs.",
  "cpc": [
    "H10D 30/6713",
    "H01L 21/823871",
    "H01L 21/823885",
    "H01L 23/535",
    "H01L 27/092",
    "H01L 29/7827",
    "H01L 29/78642",
    "H10D 30/025",
    "H10D 30/63",
    "H10D 30/6715",
    "H10D 30/6728",
    "H10D 30/6735",
    "H10D 30/6741",
    "H10D 30/675",
    "H10D 30/6757",
    "H10D 62/116",
    "H10D 62/122",
    "H10D 84/0121",
    "H10D 84/0128",
    "H10D 84/013",
    "H10D 84/0149",
    "H10D 84/0151",
    "H10D 84/016",
    "H10D 84/0167",
    "H10D 84/017",
    "H10D 84/0186",
    "H10D 84/0188",
    "H10D 84/0195",
    "H10D 84/038",
    "H10D 84/83",
    "H10D 84/85",
    "H10D 86/021",
    "H10D 86/441",
    "H10D 86/60",
    "H10W 20/054",
    "H10W 20/0698",
    "H10W 20/20"
  ],
  "ipc": [
    "H01L 21/8238",
    "H01L 27/092",
    "H01L 29/66",
    "H01L 29/78",
    "H01L 29/786",
    "H10W 20/20"
  ],
  "assignees": [
    "Taiwan Semiconductor Manufacturing Co TSMC Ltd"
  ],
  "inventors": [
    "Wai-Yi Lien",
    "Yi-Hsun CHIU",
    "Jia-Chuan You",
    "Yu-Xuan Huang",
    "Chih-Hao Wang"
  ],
  "filing_date": "2015-01-29",
  "publication_date": "2016-05-24",
  "grant_date": "2016-05-24",
  "priority_date": "2015-01-29",
  "application_number": "US-201514608958-A",
  "family_id": "55969807",
  "cited_by_count": 5,
  "citations": [
    "US20040113207A1",
    "US20070010078A1",
    "US7667271B2",
    "US20100270611A1",
    "US20110062515A1",
    "US20110068407A1",
    "US8362575B2",
    "US8610240B2",
    "US8497528B2",
    "US8729627B2",
    "US8796759B2",
    "US8440517B2",
    "US8367498B2",
    "US20130011983A1",
    "US8841701B2",
    "US8723272B2",
    "US8828823B2",
    "US8847293B2",
    "US8836016B2",
    "US8785285B2",
    "US8680576B2",
    "US8729634B2",
    "US8809139B2",
    "US8853025B2",
    "US20140252412A1"
  ]
}

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