Lowering tungsten resistivity by replacing titanium nitride with titanium silicon nitride

{
  "publication_number": "US9583349B2",
  "country": "US",
  "kind": "B2",
  "title": "Lowering tungsten resistivity by replacing titanium nitride with titanium silicon nitride",
  "abstract": "Semiconductor devices, methods and apparatus for forming the same are provided. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions. The gate electrode stack includes a conductive film layer on a gate dielectric layer, a refractory metal silicon nitride film layer on the conductive film layer, and a tungsten film layer on the refractory metal silicon nitride film layer. In one embodiment, the method includes positioning a substrate within a processing chamber, wherein the substrate includes a source and drain region, a gate dielectric layer between the source and drain regions, and a conductive film layer on the gate dielectric layer. The method also includes depositing a refractory metal silicon nitride film layer on the conductive film layer and depositing a tungsten film layer on the refractory metal silicon nitride film layer.",
  "claims": [
    "1. A method of depositing a tungsten film layer, comprising: forming a conductive film layer on a substrate; forming a titanium nitride film layer on the conductive film layer; forming a plasma in a processing region of a first chamber using an RF power supply coupled to a titanium silicon alloy target in the first chamber, the titanium silicon alloy target having a first surface that is in contact with the processing region of the first chamber and a second surface that is opposite the first surface; rotating a first magnetron about the center point of the titanium silicon alloy target; biasing a substrate support positioned in the first chamber with an RF power supply coupled to the substrate support; flowing a nitrogen-containing gas into the processing region of the first chamber; depositing a titanium silicon nitride film layer on the titanium nitride film layer while the substrate is positioned on the substrate support in the first chamber; and forming the tungsten film layer on the titanium silicon nitride film layer, wherein forming the tungsten film layer comprises: forming a plasma in a processing region of a second chamber using an RF power supply coupled to a tungsten target in the second chamber, the tungsten target having a first surface that is in contact with the processing region of the second chamber and a second surface that is opposite the first surface; rotating a second magnetron about the center point of the tungsten target; biasing a substrate support positioned in the second chamber with an RF power supply coupled to the substrate support positioned in the second chamber; and depositing the tungsten film layer on the titanium silicon nitride film layer positioned on the substrate support in the second chamber, wherein a frequency of the RF power supply coupled to the tungsten target is greater than a frequency of the RF power supply coupled to the substrate support positioned in the second chamber.",
    "2. The method of claim 1, wherein the first magnetron is disposed adjacent the second surface of the titanium silicon alloy target, the first magnetron comprising: an outer pole comprising a first plurality of magnets; and an inner pole comprising a second plurality of magnets, wherein the outer pole and the inner pole form a closed-loop magnetron assembly.",
    "3. The method of claim 2, wherein a ratio of the magnetic fields generated by the outer pole and the inner pole is between 1.56 and 0.57.",
    "4. The method of claim 1, further comprising heating the substrate support positioned in the first chamber.",
    "5. The method of claim 1 wherein the processing region of the first chamber is pressurized from 2.5 mTorr to 6.5 mTorr.",
    "6. The method of claim 4, wherein the substrate support positioned in the first chamber is heated to a temperature from 50° C. to 900° C.",
    "7. The method of claim 1, wherein the frequency of the RF power supply coupled to the titanium silicon alloy target is greater than the frequency of the RF power supply coupled to the substrate support positioned in the first chamber.",
    "8. The method of claim 1, wherein the titanium-silicon alloy target includes from 5 atomic percent to 95 atomic percent silicon and from 5 atomic percent to 95 atomic percent titanium.",
    "9. The method of claim 1, wherein the conductive film layer is a polysilicon film layer.",
    "10. The method of claim 9, further comprising forming a titanium seed layer on the conductive film layer prior to depositing the titanium nitride film layer.",
    "11. The method of claim 1, wherein the tungsten film layer has a resistivity between 11 to 12 μohms-cm."
  ],
  "description_excerpt": "Field\n\nEmbodiments of the present invention generally relate to methods and an apparatus of forming integrated circuits. More particularly, embodiments of the invention relate to methods and an apparatus for forming a gate electrode and associated layers.\n\nDescription of the Related Art\n\nIntegrated circuits may include more than one million micro-electronic devices such as transistors, capacitors, and resistors. One type of integrated circuit is field effect transistors (e.g., metal-oxide-semiconductor field effect transistors (MOSFET or MOS)) that are formed on a substrate (e.g., a semiconductor substrate) and cooperate to perform various functions within the circuit. A MOSFET transistor comprises a gate structure disposed between source and drain regions that are formed in the substrate. The gate structure generally comprises a gate electrode and a gate dielectric. The gate electrode is disposed over the gate dielectric to control a flow of charge carriers in a channel region formed between the drain and source regions beneath the gate dielectric. To increase the speed of the transistor, the gate may be formed from materials that lower the resistivity of the gate.\n\nThe gate dielectric layer may be formed of dielectric materials such as silicon dioxide (SiO 2), or a high-k dielectric material having a dielectric constant greater than 4.0, such as SiON, SiN, hafnium oxide (HfO 2), hafnium silicate (HfSiO 2), hafnium silicon oxynitride (HfSiON), zirconium oxide (ZrO 2), zirconium silicate (ZrSiO 2), barium strontium titanate (BaSrTiO 3, or BST), lead zirconate titanate (Pb(ZrTi)O 3, or PZT), and the like.",
  "cpc": [
    "H10D 64/01312",
    "H01L 21/28061",
    "H01L 21/28273",
    "H01L 21/285",
    "H01L 21/2855",
    "H01L 21/28568",
    "H01L 21/76889",
    "H01L 27/10873",
    "H01L 29/4941",
    "H01L 29/66477",
    "H01L 29/78",
    "H10B 12/05",
    "H10D 30/021",
    "H10D 30/60",
    "H10D 64/035",
    "H10D 64/664",
    "H10P 14/418",
    "H10P 14/42",
    "H10P 14/44",
    "H10W 20/066"
  ],
  "ipc": [
    "H01L 21/285",
    "H10D 30/01",
    "H10D 64/66",
    "H01L 21/768"
  ],
  "assignees": [
    "Applied Materials Inc"
  ],
  "inventors": [
    "Srinivas Gandikota",
    "Zhendong Liu",
    "Jianxin Lei",
    "Rajkumar Jakkaraju"
  ],
  "filing_date": "2014-11-25",
  "publication_date": "2017-02-28",
  "grant_date": "2017-02-28",
  "priority_date": "2012-06-27",
  "application_number": "US-201414553842-A",
  "family_id": "49777228",
  "cited_by_count": 17,
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}