Field effect transistor and method of manufacturing the same

{
  "publication_number": "US2007029577A1",
  "country": "US",
  "kind": "A1",
  "title": "Field effect transistor and method of manufacturing the same",
  "abstract": "A field effect transistor includes a first semiconductor region of a first conduction type, a gate electrode formed on the channel region of the first semiconductor region via a gate insulating film, source and drain electrodes formed to interpose the channel region, second semiconductor regions of a second conduction type formed between the source and drain electrodes and the channel region, the second semiconductor regions giving rise to an extension region of the source and drain electrodes, and third semiconductor regions of the second conduction type formed between the source and drain electrodes and each of the first and second semiconductor regions, the third semiconductor regions formed by segregation from the source and drain electrodes and having an impurity concentration higher than that of the second semiconductor regions.",
  "claims": [
    "1. A field effect transistor comprising: a first semiconductor region of a first conduction type, on which a channel region is formed; a gate electrode formed on the channel region of the first semiconductor region with a gate insulating film being formed between the gate electrode and the channel region; source and drain electrodes formed on the first semiconductor region with the channel region of the first semiconductor region being interposed between the source and drain electrodes in a channel length direction; second semiconductor regions of a second conduction type formed between each of the source and drain electrodes and the channel region, each of the second semiconductor regions forming an extension region of each of the source and drain electrodes; and third semiconductor regions of the second conduction type formed between each of the source and drain electrodes and each of the first semiconductor region and the second semiconductor region, each of the third semiconductor regions formed by segregation from the source and drain electrodes and having an impurity concentration higher than that of the second semiconductor regions.",
    "2. The field effect transistor according to claim 1, wherein the first semiconductor region is formed of a semiconductor layer formed on a buried insulating film.",
    "3. The field effect transistor according to claim 2, wherein each part of the third semiconductor regions is in direct contact with the buried insulating film.",
    "4. The field effect transistor according to claim 2, wherein a part of each of the source and drain electrodes is in direct contact with the buried insulating film.",
    "5. The field effect transistor according to claim 1, further comprising fourth semiconductor regions of the first conduction type formed between the first semiconductor region and the second semiconductor regions, and having an impurity concentration higher than that of the first semiconductor region.",
    "6. The field effect transistor according to claim 1, further comprising fifth semiconductor regions of the second conduction type formed between a bottom part of the third semiconductor regions and the first semiconductor region.",
    "7. The field effect transistor according to claim 1, wherein the gate electrode being made of Ni silicide and each of the source and drain electrodes being made of Co silicide.",
    "8. A method of manufacturing a field effect transistor, the method comprising: forming a gate electrode on a part of a first semiconductor region of a first conduction type with a gate insulating film interposed between the gate electrode and the part of the first semiconductor region; forming second semiconductor regions of a second conduction type on the first semiconductor region with the gate electrode arranged between the second semiconductor regions by ion-implanting an impurity using the gate electrode as a mask, the second semiconductor regions forming source and drain extension regions, respectively; forming sidewall insulating films on opposite side surfaces of the gate electrode after formation of the second semiconductor regions; ion-implanting an impurity to the first semiconductor region using the gate electrode and the sidewall insulating films as a mask to form ion-implanted parts; forming source and drain electrodes by siliciding selectively the first semiconductor region to an area deeper than the ion-implanted part; and forming third semiconductor regions of the second conduction type having an impurity concentration higher than that of the second semiconductor regions, in an interface between each of the source and drain electrodes and each of the first semiconductor region and the second semiconductor regions, by segregation from the source and drain electrodes.",
    "9. The manufacturing method according claim 8, further comprising: forming fourth semiconductor regions of the first conduction type having an impurity concentration higher than that of the first semiconductor region, at a position deeper than that of the second semiconductor regions, by ion-implanting a different impurity from that used to form the second impurity region in the first semiconductor region using the gate electrode as a mask immediately before or after formation of the second semiconductor regions.",
    "10. The manufacturing method according claim 8, wherein a semiconductor layer formed on a buried insulating film is used as the first semiconductor region.",
    "11. The manufacturing method according claim 10, wherein each part of the third semiconductor layers is formed between each of the source and drain electrodes and the buried insulating film by carrying out the siliciding for forming the source and drain electrodes until immediately before contacting the buried insulating film.",
    "12. The manufacturing method according claim 10, wherein the siliciding for forming the source and drain electrodes is carried out until contacting the buried insulating film.",
    "13. A field effect transistor comprising: a first semiconductor region of a first conduction type on which a channel region is formed; a gate electrode formed on the channel region of the first semiconductor region with a gate insulating film interposed between the gate electrode and the channel region; source and drain electrodes formed on the first semiconductor region with the channel region of the first semiconductor region being interposed between the source and drain electrodes in a channel length direction, the source and drain electrodes being formed of a metal silicide; and impurity segregation regions of a second conduction type formed between the first semiconductor region and each of the source and drain electrodes, the impurity segregations region being formed by segregation of the impurity into the metal silicide.",
    "14. The field effect transistor according to claim 13, further comprising second semiconductor regions of a second conduction type formed between each of the source and drain electrodes and the first semiconductor region.",
    "15. The field effect transistor according to claim 13, wherein the first semiconductor region is formed of a semiconductor layer formed on a buried insulating film.",
    "16. The field effect transistor according to claim 15, wherein each part of the impurity segregation regions is in direct contact with the buried insulating film.",
    "17. The field effect transistor according to claim 13, further comprising third semiconductor regions of the first conduction type formed between the impurity segregation regions and the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region.",
    "18. The field effect transistor according to claim 13, wherein the gate electrode being made of Ni silicide and each of the source and drain electrodes being made of Co silicide.",
    "19. A method of manufacturing a field effect transistor, the method comprising: forming a gate electrode on a part of a first semiconductor region of a first conduction type with a gate insulating film interposed between the gate electrode and the first semiconductor region; forming sidewall insulating films on opposite sides of the gate electrode; forming second semiconductor regions of a second conduction type in the first semiconductor region by ion-implanting an impurity to the first semiconductor region using the gate electrode and the sidewall insulating films as a mask; slimming or removing the sidewall insulating films after the formation of the second semiconductor regions; adding an impurity of a second conduction type in an area of a surface portion of the first semiconductor region to a level shallower than the second semiconductor regions using the gate electrode as a mask after slimming or removing the sidewall insulating films; and forming source and drain electrodes by siliciding selectively the surface portion of the first semiconductor region, where the second conduction type impurity is added, and forming segregation regions of the second conduction type between the first semiconductor region and each of the source and drain electrodes by segregation of the impurity into the source and drain electrodes."
  ],
  "description_excerpt": "1. Field of the Invention\n\nThe present invention relates to a semiconductor device, and more specifically to a metal-insulator semiconductor (MIS) type field effect transistor with improved source and drain regions as well as a method of manufacturing such a transistor.\n\n2. Description of the Related Art\n\nIn order to upgrade the performance of semiconductor integrated circuits, it is essential to improve the performance of the field effect transistor, which is a structural element of each circuit. The guiding principle to achieve a higher performance of an element is the scaling, and the performance of an element has been improved by microfabrication technique. At the same time, as the microfabrication techniques advances, there rise further technical obstacles to be solved. According to the International Semiconductor Roadmap, there are even no signs of a solution for a 10-to-20 nm junction (drain extension part) of the 65-nm generation, particularly, in the source-drain part formation technique.\n\nA serious problem in the technical development of the source-drain part is the junction leak (JL). That is, in order to suppress the punch through in transistors of the 65-nm generation, it is necessary to make the diffusion layer sufficiently shallow. However, at the same time, if the depth of the diffusion layer is decreased to such a level, an increasing of junction leak due to silicide occur at, in particular, the edge of the gate.",
  "cpc": [
    "H10D 62/151",
    "H10D 30/0227",
    "H10D 30/0323",
    "H10D 30/601",
    "H10D 30/62",
    "H10D 30/6706",
    "H10D 30/6737",
    "H10D 30/6743",
    "H10D 64/0132",
    "H10D 64/015"
  ],
  "ipc": [
    "H01L 29/76"
  ],
  "assignees": [
    "Toshiba Corp"
  ],
  "inventors": [
    "Atsuhiro Kinoshita",
    "Junji Koga"
  ],
  "filing_date": "2006-05-25",
  "publication_date": "2007-02-08",
  "priority_date": "2005-08-02",
  "application_number": "US-44015006-A",
  "family_id": "37700283",
  "cited_by_count": 11,
  "citations": [
    "US5880500A",
    "US6891235B1",
    "US20030119247A1",
    "US7170084B1",
    "US20050093033A1"
  ]
}