Semiconductor memory device including a floating gate having an undoped edge portion proximate to a source portion of the memory device

{
  "publication_number": "US5446298A",
  "country": "US",
  "kind": "A",
  "title": "Semiconductor memory device including a floating gate having an undoped edge portion proximate to a source portion of the memory device",
  "abstract": "The present invention provides a semiconductor device including nonvolatile memories and a manufacturing method thereof which have advantages in reliability of writing operation and in erasing time of erasing operation. This semiconductor device comprises a silicon substrate 40, a N type drain 40 formed in the surface of the substrate 36, a N type source 36, a tunnel oxide layer 14 located on the surface of the substrate, and a floating gate located on the tunnel oxide layer 14, having a first portion 55 in side of the source 36 and a second portion 54 in both sides of the drain 40 and the substrate 2, the second portion 54 being of a lower N type dosage than the first portion 55.",
  "claims": [
    "1. A semiconductor device including nonvolatile memories comprising: a) a substrate of semiconductor; b) a drain of a first conductivity type located in the surface of the substrate; c) a source of the first conductivity type located in the surface of the substrate so that the substrate defines a space between the drain and the source; d) a first insulating layer located on the surface of the substrate; e) a floating gate located on the first insulating layer, the floating gate having an upper region and a lower region under the upper region, the lower region having top portion proximate to the upper region, a bottom edge portion opposite the top portion, a first edge portion at a first side proximate to the source and a second edge portion at a second side opposite the first side and proximate to the drain, the first edge portion being doped, the second edge portion being injected with substantially no dopant; f) a second insulating layer located on the floating gate; and g) a control electrode located on the second insulating layer.",
    "2. A semiconductor device including nonvolatile memories according to claim 1, wherein the drain is a N+ type region.",
    "3. A semiconductor device including nonvolatile memories according to claim 1, wherein the drain is a P+ type region.",
    "4. A semiconductor device including nonvolatile memories according to claim 1, wherein the source is comprised of a N+ type region and a N- type region surrounding the N+ type region.",
    "5. A semiconductor device including nonvolatile memories according to claim 1, wherein the source is comprised of a P+ type region and a P- type region surrounding the P+ type region.",
    "6. A semiconductor device including nonvolatile memories according to claim 4, wherein the upper portion of the floating gate is comprised of a N+ type region.",
    "7. A semiconductor device including nonvolatile memories according to claim 6, wherein the first portion of the floating gate is comprised of a N- type region.",
    "8. A semiconductor device including nonvolatile memories according to claim 7, wherein the N- type regions are formed by ion implanting using phosphorous as a dopant, and the N+ type regions are formed by ion implanting using arsenic as a dopant.",
    "9. A semiconductor device including nonvolatile memories according to claim 2, wherein the source is comprised of a N+ type region and a N- type region surrounding the N+ type region.",
    "10. A semiconductor device including nonvolatile memories according to claim 3, wherein the source is comprised of a P+ type region and a P- type region surrounding the P+ type region.",
    "11. A semiconductor device including nonvolatile memories manufactured by a method including the following steps: a) forming a first insulating layer on a substrate of semiconductor, b) forming a first polysilicon layer on the first insulating layer, c) implanting a dopant of a first diffusion coefficient so as to be diffused into only an upper side of the first polysilicon layer, d) forming a second insulating layer on the first polysilicon layer, e) forming a second polysilicon layer on the second insulating layer, f) forming plural stacking layers having side surfaces on the substrate by etching the first insulating layer, the first polysilicon layer, the second insulating layer, and the second polysilicon layer, g) implanting a dopant of a second diffusion coefficient into the substrate, the dopant being implanted into the substrate with a certain angle from vertical against the substrate using a resist as a mask, the dopant being diffused in the substrate so as to form a source and such that in the semiconductor device, the dopant is diffused in only one side surface of the plural stacking layer proximate to the source and opposite another side surface of the plural stacking layer proximate to a drain, and h) implanting a dopant of the first diffusion coefficient vertically against the substrate after removing the resist to form the drain proximate to the another side surface of the plural stacking layers and to further form the source.",
    "12. A semiconductor device including nonvolatile memories according to claim 11, wherein the first diffusion coefficient is smaller than the second diffusion coefficient.",
    "13. A semiconductor device including nonvolatile memories according to claim 12, wherein the dopant of the first diffusion coefficient is arsenic, and wherein the dopant of the second coefficient of diffusion is phosphorous."
  ],
  "description_excerpt": "This is a continuation of application Ser. No. 08/92,892, filed on Jul. 19, 1993, which was abandoned upon the filing hereof.\n\n1. Field of the Invention\n\nThe present invention relates to a semiconductor device and, more particularly, a semiconductor device including nonvolatile memories.\n\n2. Description of the Related Art\n\nNowadays, an electrically erasable programmable read only memory (E 2 PROM) of flash type (flash memory hereafter) is known as memory where data is able to be rewritten by using electricity.\n\nThe flash memory having a control gate electrode, a floating gate electrode, a source and a drain is characterized in that data stored in the floating gate can be electrically erased using a thinner gate insulating layer between the floating gate and the source or drain.\n\nA conventional method for manufacturing this flash memory will be described below.\n\nReferring to FIG. 1A, an entire surface of a silicon substrate 2 is oxidized to form a silicon oxide layer 4 on the silicon substrate 2.\n\nReferring to FIG. 1B, field oxide layers 10 are formed in the entire surface of the silicon oxide layer by Local Oxidation of Silicon (LOCOS) technique to divide the substrate 2 into the plural insulated islands 12.\n\nThe substrate 2 is subjected to a injection step to adjust conductivity of what is to be channel regions.\n\nThe resulting substrate 2 is subjected to a heat treatment to form the surface of the insulated islands 12 into the tunnel oxide layer 14. A first polysilicon layer 16 is applied on the resulting substrate 2 using chemical vapor deposition (CVD) technique as shown in FIG. 1C.",
  "cpc": [
    "H10D 30/0411",
    "H10D 30/685"
  ],
  "ipc": [
    "H01L 21/336",
    "H01L 21/8247",
    "H01L 29/788",
    "H01L 29/792"
  ],
  "assignees": [
    "Rohm Co Ltd"
  ],
  "inventors": [
    "Mitsuo Kojima"
  ],
  "filing_date": "1994-09-06",
  "publication_date": "1995-08-29",
  "grant_date": "1995-08-29",
  "priority_date": "1992-07-22",
  "application_number": "US-30093494-A",
  "family_id": "16341806",
  "cited_by_count": 12,
  "citations": [
    "JPS59124161A",
    "US4742491A",
    "JPH01232765A",
    "US4994873A",
    "US5241202A"
  ]
}