Semiconductor device and method for fabricating the same

{
  "publication_number": "US9331200B1",
  "country": "US",
  "kind": "B1",
  "title": "Semiconductor device and method for fabricating the same",
  "abstract": "A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; and forming a first epitaxial layer, a second epitaxial layer, and a silicide layer in the substrate adjacent to the gate structure. Preferably, the first epitaxial layer, the second epitaxial layer, and the silicide layer comprise SiGeSn.",
  "claims": [
    "1. A method for fabricating semiconductor device, comprising: providing a substrate having a gate structure thereon; and forming a first epitaxial layer, a second epitaxial layer, and a silicide layer in the substrate adjacent to the gate structure, wherein the first epitaxial layer, the second epitaxial layer, and the silicide layer comprise SiGeSn, and the content of Ge and Sn in the first epitaxial layer is between 15-30 atomic percentage.",
    "2. The method of claim 1, further comprising: forming a spacer adjacent to the gate structure; forming a recess in the substrate adjacent to the spacer; forming the first epitaxial layer in the recess; forming the second epitaxial layer on the first epitaxial layer; forming a third epitaxial layer on the second epitaxial layer; and performing a silicide process to transform the third epitaxial layer into the silicide layer.",
    "3. The method of claim 2, further comprising performing in-situ p+ doping process while forming the first epitaxial layer, the second epitaxial layer, or the third epitaxial layer.",
    "4. The method of claim 1, wherein the content of Ge and Sn in the second epitaxial layer is between 50-80 atomic percentage.",
    "5. The method of claim 1, wherein the content of Ge and Sn in the third epitaxial layer is between 15-30 atomic percentage.",
    "6. The method of claim 1, wherein the silicide layer comprises Ni(SiGeSn).",
    "7. A semiconductor device, comprising: a substrate having a gate structure thereon; a first epitaxial layer in the substrate adjacent to the gate structure; a second epitaxial layer on the first epitaxial layer; and a silicide layer on the second epitaxial layer, wherein the first epitaxial layer, the second epitaxial layer, and the silicide layer comprise SiGeSn, and the content of Ge and Sn in the first epitaxial layer is between 15-30 atomic percentage.",
    "8. The semiconductor device of claim 7, further comprising: a spacer adjacent to the gate structure; the first epitaxial layer in the substrate adjacent to the spacer; the second epitaxial layer on the first epitaxial layer; and the silicide layer on the second epitaxial layer.",
    "9. The semiconductor device of claim 7, wherein the content of Ge and Sn in the second epitaxial layer is between 50-80 atomic percentage.",
    "10. The semiconductor device of claim 7, wherein the content of Ge and Sn in the third epitaxial layer is between 15-30 atomic percentage.",
    "11. The semiconductor device of claim 7, wherein the silicide layer comprises Ni(SiGeSn)."
  ],
  "description_excerpt": "1. Field of the Invention\n\nThe invention relates to a method for fabricating semiconductor device, and more particularly, to a method of forming epitaxial layers containing SiGeSn alloys.\n\n2. Description of the Prior Art\n\nIn order to increase the carrier mobility of semiconductor structure, it has been widely used to apply tensile stress or compressive stress to a gate channel. For instance, if a compressive stress were to be applied, it has been common in the conventional art to use selective epitaxial growth (SEG) technique to form epitaxial structure such as silicon germanium (SiGe) epitaxial layer in a silicon substrate. As the lattice constant of the SiGe epitaxial layer is greater than the lattice constant of the silicon substrate thereby producing stress to the channel region of PMOS transistor, the carrier mobility is increased in the channel region and speed of MOS transistor is improved accordingly. Conversely, silicon carbide (SiC) epitaxial layer could be formed in silicon substrate to produce tensile stress for gate channel of NMOS transistor.\n\nDespite the aforementioned approach improves the carrier mobility in the channel region, strain of the device cannot be increased significantly as the size of the device decreases to lower electrical resistance in the source/drain region and reach desirable driving current. Hence, how to improve the current fabrication flow has become an important task in this field.\n\nAccording to a preferred embodiment of the present invention, a method for fabricating semiconductor device is disclosed.",
  "cpc": [
    "H10D 30/797",
    "H01L 29/161",
    "H01L 29/41783",
    "H01L 29/45",
    "H01L 29/665",
    "H01L 29/66568",
    "H01L 29/7848",
    "H10D 30/0212",
    "H10D 30/027",
    "H10D 62/021",
    "H10D 62/832",
    "H10D 64/259"
  ],
  "ipc": [
    "H01L 29/161",
    "H01L 29/417",
    "H01L 29/45",
    "H01L 29/66",
    "H01L 29/78"
  ],
  "assignees": [
    "United Microelectronics Corp"
  ],
  "inventors": [
    "Lanxiang Wang",
    "Hong Liao",
    "Chao Jiang",
    "Duan Quan Liao",
    "Ye Chao Li"
  ],
  "filing_date": "2015-01-06",
  "publication_date": "2016-05-03",
  "grant_date": "2016-05-03",
  "priority_date": "2014-12-19",
  "application_number": "US-201514590008-A",
  "family_id": "55807614",
  "cited_by_count": 400,
  "citations": [
    "US20100193882A1",
    "US20140239416A1",
    "US20140197376A1",
    "US20140053894A1"
  ]
}