Methods of forming a contact structure for a vertical channel semiconductor device and the resulting device

{
  "publication_number": "US9741847B2",
  "country": "US",
  "kind": "B2",
  "title": "Methods of forming a contact structure for a vertical channel semiconductor device and the resulting device",
  "abstract": "One illustrative method disclosed includes, among other things, forming a vertically oriented semiconductor structure above a doped well region defined in a semiconductor substrate, the semiconductor structure comprising a lower source/drain region and an upper source/drain region, wherein the lower source/drain region physically contacts the upper surface of the substrate, forming a counter-doped isolation region in the substrate, forming a metal silicide region in the substrate above the counter-doped isolation region, wherein the metal silicide region is in physical contact with the lower source/drain region, and forming a lower source/drain contact structure that is conductively coupled to the metal silicide region.",
  "claims": [
    "1. A method of forming a vertically oriented transistor device, comprising: forming a semiconductor structure above a doped well region defined in a semiconductor substrate, said semiconductor structure having a long axis that is oriented approximately vertical to an upper surface of said substrate, said semiconductor structure comprising a lower source/drain region and an upper source/drain region, at least a portion of which is positioned vertically above said lower source/drain region, wherein said lower source/drain region physically contacts said upper surface of said substrate; forming a counter-doped isolation region in said substrate, wherein said counter-doped isolation region is doped opposite to said doped well region, and wherein said counter-doped isolation region separates and isolates an upper portion of said doped well region that is positioned above said counter-doped isolation region from a lower portion of said doped well region that is positioned below said counter-doped isolation region; forming a metal silicide region in said isolated upper portion of said doped well region above said counter-doped isolation region, wherein said metal silicide region is in physical contact with said lower source/drain region; and forming a lower source/drain contact structure that is conductively coupled to said metal silicide region.",
    "2. The method of claim 1, further comprising, after forming said lower source/drain contact structure, forming an upper source/drain contact structure that is conductively coupled to said upper source/drain region.",
    "3. The method of claim 1, wherein said counter-doped isolation region has an inner perimeter that surrounds and forms an interface with said isolated upper portion of said doped well region and wherein forming said metal silicide region comprises forming said metal silicide region within an area defined by said inner perimeter of said counter-doped isolation region.",
    "4. The method of claim 1, wherein forming said metal silicide region comprises forming said metal silicide region such that it is in physical contact with an entire bottom surface of said lower source/drain region.",
    "5. The method of claim 1, wherein forming said lower source/drain contact structure comprises forming said lower source/drain contact structure such that a lateral spacing between said lower source/drain contact structure and said lower source/drain region at an upper surface of said metal silicide region falls within a range of 5-50 nm.",
    "6. The method of claim 1, wherein the method further comprises forming a gate structure all around a portion of said semiconductor structure between said lower source/drain region and said upper source/drain region.",
    "7. The method of claim 6, further comprising, after forming said lower source/drain contact structure, performing at least one common process operation to form an upper source/drain contact structure that is conductively coupled to said upper source/drain region and a gate contact structure that is conductively coupled to said gate structure.",
    "8. The method of claim 1, wherein forming said counter-doped isolation region comprises performing an ion implantation process through an opening in a patterned layer of insulating material to implant dopant atoms into said substrate and performing an anneal process to activate said implanted dopant atoms.",
    "9. The method claim 1, wherein, after forming said counter-doped isolation region and prior to forming said metal silicide region, the method further comprises performing an amorphization implant process to define an amorphous region in said substrate that is positioned above said counter-doped isolation region.",
    "10. The method claim 1, wherein said counter-doped isolation region has an inner perimeter that surrounds and forms an interface with said isolated upper portion of said doped well region and wherein, after forming said counter-doped isolation region and prior to forming said metal silicide region, the method further comprises performing an amorphization implant process to define an amorphous region in said substrate within an area defined by said inner perimeter of said counter-doped isolation region.",
    "11. The method of claim 1, wherein forming said metal silicide region comprises depositing a layer of refractory metal on said substrate and performing an anneal process at a temperature that falls within a range of about 350-600° C. for a duration of about 5-100 seconds.",
    "12. A method of forming a vertically oriented transistor device, comprising: forming a semiconductor structure above a doped well region defined in a semiconductor substrate, said semiconductor structure having a long axis that is oriented approximately vertical to an upper surface of said substrate, said semiconductor structure comprising a lower source/drain region and an upper source/drain region, at least a portion of which is positioned vertically above said lower source/drain region, wherein said lower source/drain region physically contacts said upper surface of said substrate; forming a counter-doped isolation region in said doped well region, wherein said counter-doped isolation region has an outer perimeter and is doped opposite to said doped well region, and wherein said counter-doped isolation region separates and isolates an upper portion of said doped well region that is positioned between said counter-doped isolation region and said upper surface of said substrate from a lower portion of said doped well region that is positioned outside of said outer perimeter; performing an amorphization implant process to define an amorphous region within said isolated upper portion of said doped well region; forming a metal silicide region in said amorphous region above said counter-doped isolation region, wherein said metal silicide region is in physical contact with said lower source/drain region; and forming a lower source/drain contact structure that is conductively coupled to said metal silicide region.",
    "13. The method of claim 12, wherein said counter-doped isolation region has an inner perimeter that defines an outer boundary of said isolated upper portion of said doped well region and wherein forming said metal silicide region in said amorphous region comprises forming said metal silicide region within an area defined by said inner perimeter of said counter-doped isolation region.",
    "14. The method of claim 12, wherein forming said metal silicide region comprises forming said metal silicide region such that it is in physical contact with an entire bottom surface of said lower source/drain region.",
    "15. The method of claim 12, wherein forming said lower source/drain contact structure comprises forming said lower source/drain contact structure such that a lateral spacing between said lower source/drain contact structure and said lower source/drain region at an upper surface of said metal silicide region falls within a range of 5-50 nm.",
    "16. The method of claim 12, wherein forming said metal silicide region comprises depositing a layer of refractory metal on said amorphous region and performing an anneal process at a temperature that falls within a range of about 350-600° C. for a duration of about 5-100 seconds.",
    "17. A vertically oriented transistor device, comprising: a semiconductor substrate comprising a doped well region defined in said semiconductor substrate a semiconductor structure positioned above said doped well region, said semiconductor structure having a long axis that is oriented approximately vertical to an upper surface of said substrate, wherein said semiconductor structure comprises a lower source/drain region and an upper source/drain region, at least a portion of said upper source/drain region being positioned vertically above said lower source/drain region, wherein said lower source/drain region physically contacts said upper surface of said substrate; a counter-doped isolation region positioned in and doped opposite to said doped well region, wherein said counter-doped isolation region separates and isolates an upper portion of said doped well region from a lower portion of said doped well region; a metal silicide region located in said isolated upper portion of said doped well region above said counter-doped isolation region, wherein said metal silicide region is in physical contact with said lower source/drain region; and a lower source/drain contact structure that is conductively coupled to said metal silicide region.",
    "18. The device of claim 17, further comprising an upper source/drain contact structure that is conductively coupled to said upper source/drain region.",
    "19. The device of claim 17, wherein said counter-doped isolation region has an inner perimeter and wherein said metal silicide region is positioned in said upper isolated portion of said doped well region within an area defined by said inner perimeter of said counter-doped isolation region.",
    "20. The device of claim 17, wherein said metal silicide region is in physical contact with an entire bottom surface of said lower source/drain region.",
    "21. The device of claim 17, wherein a lateral spacing between said lower source/drain contact structure and said lower source/drain region at an upper surface of said metal silicide region falls within a range of 5-50 nm.",
    "22. The device of claim 17, further comprising a gate structure positioned all around a portion of said semiconductor structure between said lower source/drain region and said upper source/drain region.",
    "23. The method of claim 1, wherein said counter-doped isolation region extends upward to said upper surface of said semiconductor substrate and completely surrounds said isolated upper portion of said doped well region."
  ],
  "description_excerpt": "1. Field of the Invention\n\nThe present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming a contact structure for a vertical channel semiconductor device and the resulting device.\n\n2. Description of the Related Art\n\nIn modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially field effect transistors (FETs), are provided and operated on a restricted chip area. FETs come in a variety of different configurations, e.g., planar devices, FinFET devices, omega gate devices, gate-all-around (GAO) devices, such as nanowire devices, etc. These FET devices are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.\n\nThe channel structure of these various FET devices may be oriented substantially horizontal or substantially vertical relative to a reference planar upper surface of a semiconductor substrate. In FETs with a horizontally oriented channel structure, the current passing through the channel region of the device (when the device is “ON”) travels in a direction that is substantially parallel to the reference planar upper surface of the semiconductor substrate.",
  "cpc": [
    "H10D 30/63",
    "H01L 21/26506",
    "H01L 21/26513",
    "H01L 21/761",
    "H01L 29/0646",
    "H01L 29/41741",
    "H01L 29/41766",
    "H01L 29/42356",
    "H01L 29/45",
    "H01L 29/66666",
    "H01L 29/7827",
    "H10D 30/025",
    "H10D 62/114",
    "H10D 64/252",
    "H10D 64/256",
    "H10D 64/512",
    "H10D 64/62",
    "H10P 30/204",
    "H10P 30/208",
    "H10P 30/21",
    "H10P 30/28",
    "H10W 10/031",
    "H10W 10/30"
  ],
  "ipc": [
    "H01L 29/06",
    "H01L 29/417",
    "H01L 29/423",
    "H01L 29/45",
    "H01L 29/66",
    "H01L 29/78",
    "H10W 10/30",
    "H01L 21/336"
  ],
  "assignees": [
    "GlobalFoundries Inc"
  ],
  "inventors": [
    "Bartlomiej Jan Pawlak"
  ],
  "filing_date": "2015-11-30",
  "publication_date": "2017-08-22",
  "grant_date": "2017-08-22",
  "priority_date": "2015-11-30",
  "application_number": "US-201514953874-A",
  "family_id": "58777326",
  "cited_by_count": 3,
  "citations": [
    "US20110068418A1",
    "US20150333152A1"
  ]
}