Method of making a disposable corner etch stop-spacer for borderless contacts

{
  "publication_number": "US5759867A",
  "country": "US",
  "kind": "A",
  "title": "Method of making a disposable corner etch stop-spacer for borderless contacts",
  "abstract": "A borderless contact method for a semiconductor device is disclosed employing a disposable etch stopping spacer to protect the upper edges of adjacent structure during contact hole etching. An exemplary FET gate structure is formed on a substrate adjacent to a source or drain diffusion region. A layer of dielectric material is deposited over the structure including the gate stack. An etch stopping spacer, of a material selectively etchable relative to the dielectric material is placed upon the sidewalls and the upper edges of the gate stack. The resulting structure is blanketed with a glass layer which is selectively masked and etched to provide a hole for making a borderless contact to the substrate adjacent to the gate stack. The spacer itself can be etched away prior to filling the hole with contact material in order to maximize the contact area.",
  "claims": [
    "1. A method for making a borderless contact to a first surface of a semiconductor device in which the upper edges of structure adjacent to the site of said contact area are protected during contact hole etching, said method comprising forming semiconductor device structure adjacent said site, covering said structure including said site with a first layer of insulating material, covering said first layer of insulating material with a second layer of material, anisotropically etching said second layer of material so as to remove said second layer of material from all parallel surfaces of said first layer of insulating material and leaving said second layer of material on all perpendicular surfaces of said first layer of insulating material, parallel and perpendicular being relative to said first surface of said semiconductor device, placing a third layer of material on the resulting structure including said perpendicular portions of said second layer of material, said third layer of material being selectively etchable relative to said second layer of material, masking said third layer of material to expose said site, anisotropically etching said third layer of material at said exposed site down to said first layer of insulating material covering said structure including said site using said second layer of material as an etch stop, removing said first layer of insulating material and any underlying layer at said site to expose said first surface.",
    "2. The method defined in claim 1 wherein said first layer of insulating material is silicon nitride, said second layer of material is polysilicon, and said third layer of material is borophosphosilicate glass.",
    "3. The method defined in claim 1 wherein said structure adjacent to said site is the gate of an FET comprising an uppermost layer of silicon nitride.",
    "4. The method defined in claim 1 wherein said second layer of material is selected from the material group comprising polysilicon, boron nitride, and undoped silicon dioxide.",
    "5. The method defined in claim 2 and further including oxidizing said second layer of material remaining on vertical surfaces other than at said site prior to removing said first layer of insulating material.",
    "6. The method defined in claim 1 wherein the materials comprising said first layer of insulating material and said second layer of material are selectively etchable relative to each other.",
    "7. The method defined in claim 1 wherein the materials comprising said first, layer of insulating material, said second and third layers of material are selectively etchable relative to each other.",
    "8. The method defined in claim 1 and further including removing said second layer of material at said site prior to removing said first layer of insulating material at said site."
  ],
  "description_excerpt": "The present invention generally relates to very high packing density microelectronic chip devices and, more particularly, to the use of borderless contacts in such devices.\n\nIn the formation of semiconductor devices, it is necessary to provide desired electrical contact between certain devices and to prevent unwanted contact with other devices while doing so in a manner that does not compromise high device packing density on the chip. In order to provide a margin for error in the alignment accuracy of the successive mask levels used in the fabrication of such chips, whereby wanted contact locations are established and unwanted contacts are avoided, border regions had been provided around mask contact locations. Although the border regions proved helpful, they required the allocation and sacrifice of chip surface area which limits the maximum number of integrated circuits that can be packed into a given area.\n\nA number of borderless contact processes have been developed to prevent unwanted and inadvertent contacts without the costly expenditure of chip \"real estate\" inherent in the allocation of contact border regions. These considerations are well understood in the art and are discussed in more detail, for example, in U.S. Pat. No. 4,966,870, issued Oct. 30, 1990, to Jeffrey R. Barber, et al and assigned to the present assignee.\n\nBorderless contact techniques differ in complexity and efficacy. They generally provide for a desired contact area to overlay a potential undesired contact region, such as, for example, where source and drain contacts of a field effect transistor are allowed to partially overlap the gate region.",
  "cpc": [
    "H10D 64/011",
    "H10D 64/0111",
    "H10W 20/01",
    "Y10S 438/97"
  ],
  "ipc": [
    "H01L 21/336",
    "H01L 29/78",
    "H10P 14/40"
  ],
  "assignees": [
    "International Business Machines Corp"
  ],
  "inventors": [
    "Michael D. Armacost",
    "Jeffrey Peter Gambino"
  ],
  "filing_date": "1995-04-21",
  "publication_date": "1998-06-02",
  "grant_date": "1998-06-02",
  "priority_date": "1995-04-21",
  "application_number": "US-42729695-A",
  "family_id": "23694267",
  "cited_by_count": 23,
  "citations": [
    "US5543360A",
    "US5466637A",
    "US5496771A",
    "US5482894A",
    "US5525552A"
  ]
}