Semiconductor structures with coplanar recessed gate layers and fabrication methods

{
  "publication_number": "US9252238B1",
  "country": "US",
  "kind": "B1",
  "title": "Semiconductor structures with coplanar recessed gate layers and fabrication methods",
  "abstract": "Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.",
  "claims": [
    "1. A method comprising: fabricating a semiconductor structure, the fabricating comprising: providing a gate structure over a semiconductor substrate, the gate structure comprising multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, wherein upper surfaces of the recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.",
    "2. The method of claim 1, wherein the providing comprises providing at least one conformal gate layer of the multiple conformal gate layers, and the recessing comprises recessing a portion of the at least one conformal gate layer of the multiple conformal gate layers, prior to removing the gate material disposed within the gate structure.",
    "3. The method of claim 1, wherein the multiple conformal gate layers comprise a gate dielectric layer disposed conformally within the gate structure, and a work-function layer disposed conformally above the gate dielectric layer, and the recessing comprises recessing a portion of the work-function layer from within the gate structure, prior to recessing the gate dielectric layer.",
    "4. The method of claim 3, wherein the recessed, multiple conformal gate layer comprises one of a recessed work-function layer or a recessed gate dielectric layer.",
    "5. The method of claim 3, wherein the recessing comprises performing a first recessing process, and performing a second recessing process, the first recessing process being performed over the work-function layer, and the second recessing process being performed over the gate dielectric layer.",
    "6. The method of claim 5, wherein the first recessing process being performed at a first time interval, and the method further comprises performing the second recessing process at a second time interval, the first time interval and the second time interval being different time intervals, and the second time interval being longer than the first time interval.",
    "7. The method of claim 5, wherein the recessing further comprises performing the first recessing process of the work-function layer, and performing the second recessing process of the gate dielectric layer using same etching chemistries.",
    "8. The method of claim 7, wherein the same etching chemistries are performed employing boron trichloride gas.",
    "9. The method of claim 3, wherein the gate dielectric layer comprises a high-k gate dielectric layer, and wherein the work-function layer comprises a metal work-function layer.",
    "10. The method of claim 1, wherein the method comprises recessing of the multiple conformal gate layers being performed using a first etching chemistry, and removing of the gate material being performed using a second etching chemistry, the first etching chemistry and the second etching chemistry employing different etching chemistries.",
    "11. The method of claim 10, wherein the first etching chemistry being performed employing boron trichloride, and the second etching chemistry being performed employing silicon tetrachloride.",
    "12. The method of claim 1, wherein the gate material comprises a metal gate material.",
    "13. A structure comprising: a semiconductor structure, the semiconductor structure comprising: a semiconductor substrate; a gate structure disposed over the semiconductor substrate, the gate structure comprising recessed, multiple conformal gate layers, wherein multiple conformal gate layers are recessed below an upper surface of the gate structure, and upper surfaces of the recessed, multiple conformal gate layers are coplanar; and a recessed gate material disposed within the recessed, conformal gate layers, wherein an upper surface of the recessed gate material is coplanar with the upper surfaces of the recessed, multiple conformal gate layers.",
    "14. The structure of claim 13, wherein the recessed, multiple conformal gate layers comprise a recessed gate dielectric layer, and wherein the structure further comprises a recessed work-function layer disposed over the recessed gate dielectric layer, an upper surface of the gate dielectric layer being coplanar with an upper surface of the recessed work-function layer.",
    "15. The structure of claim 14, wherein the recessed gate dielectric layer comprises a high-k gate dielectric layer, and wherein the recessed work-function layer comprises a metal work-function layer.",
    "16. The structure of claim 13, wherein the recessed gate material comprises a metal gate material.",
    "17. A structure comprising: a semiconductor structure, the semiconductor structure comprising: a semiconductor substrate; a gate structure disposed over the semiconductor substrate, the gate structure comprising recessed, multiple conformal gate layers, wherein multiple conformal gate layers are recessed below an upper surface of the gate structure, and upper surfaces of the recessed, multiple conformal gate layers are coplanar; and a gate material disposed within the recessed, multiple conformal gate layers, wherein an uppermost surface of the gate material is disposed above the upper surface of the gate structure.",
    "18. The structure of claim 17, wherein the recessed, multiple conformal gate layers comprise a recessed gate dielectric layer, and wherein the structure further comprises a recessed work-function layer disposed over the recessed gate dielectric layer, an upper surface of the gate dielectric layer being coplanar with an upper surface of the recessed work-function layer.",
    "19. The structure of claim 17, wherein the recessed gate dielectric layer comprises a high-k gate dielectric layer, and wherein the recessed work-function layer comprises a metal work-function layer.",
    "20. The structure of claim 17, wherein the gate material comprises a metal gate material, and the structure further comprises the upper surface of the gate material being disposed above the upper surface of the recessed, at least one conformal gate layer."
  ],
  "description_excerpt": "Semiconductor structures, such as semiconductor devices or integrated circuits are typically fabricated in large batches from a semiconductor wafer. An integrated circuit fabrication typically involves a process of depositing a conductive material into appropriately configured openings in an intermediate circuit structure, for instance, to facilitate forming gate structures and/or contact structures of the transistors. This process being often referred to as gate metallization or contact metallization processing. As the integration density of transistors continues to increase, it is desirable to reduce or minimize defects within the gate structures and/or contact structures, in order to maximize fabrication efficiency and enhance commercial advantage.\n\nThe shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, of a method which includes fabricating a semiconductor structure. The fabricating includes: providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with the recessed, multiple conformal gate layers.",
  "cpc": [
    "H10D 64/017",
    "H01L 21/32135",
    "H01L 29/401",
    "H01L 29/4966",
    "H01L 29/517",
    "H01L 29/66545",
    "H10D 64/013",
    "H10D 64/01318",
    "H10D 64/01342",
    "H10D 64/513",
    "H10D 64/667",
    "H10D 64/691",
    "H10P 50/267",
    "H10P 50/283",
    "H10P 50/285"
  ],
  "ipc": [
    "H01L 21/3213",
    "H10D 30/01",
    "H10D 64/00",
    "H10D 64/27",
    "H10D 64/66",
    "H10D 64/68"
  ],
  "assignees": [
    "GlobalFoundries Inc",
    "Lam Research Corp"
  ],
  "inventors": [
    "Kristina Trevino",
    "Yuan-Hung Liu",
    "Gabriel Padron Wells",
    "Xing Zhang",
    "Hoong Shing Wong",
    "Chang Ho Maeng",
    "Taejoon Han",
    "Gowri Kamarthy",
    "Isabelle Orain",
    "Ganesh Upadhyaya"
  ],
  "filing_date": "2014-08-18",
  "publication_date": "2016-02-02",
  "grant_date": "2016-02-02",
  "priority_date": "2014-08-18",
  "application_number": "US-201414461887-A",
  "family_id": "55175036",
  "cited_by_count": 430,
  "citations": [
    "US20030062568A1",
    "US20130049072A1",
    "US8951855B2",
    "US20130320412A1",
    "US20140217482A1"
  ]
}