Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same

{
  "publication_number": "US9324811B2",
  "country": "US",
  "kind": "B2",
  "title": "Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same",
  "abstract": "Structures including a tensile-stressed silicon arsenic layer, devices including the structures, and methods of forming the devices and structures are disclosed. Exemplary tensile-stressed silicon arsenic layer have an arsenic doping level of greater than 5 E+20 arsenic atoms per cubic centimeter. The structures can be used to form metal oxide semiconductor devices.",
  "claims": [
    "1. A method of forming a tensile-stressed silicon arsenic layer, the method comprising the steps of: supporting a substrate comprising silicon in a reactor, wherein a surface of the substrate is exposed to a reaction region within the reactor; supplying a silicon source to the reactor; supplying an arsenic source to the reactor; and at a pressure between about 90 Torr and about 300 Torr, forming the tensile-stressed silicon arsenic layer having a concentration of arsenic of greater than 1 E+21 arsenic atoms/cubic centimeter on the surface.",
    "2. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein during the step of forming the tensile-stressed silicon arsenic layer, a temperature of the reaction region is between 500° C. and 700° C.",
    "3. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein during the step of forming the tensile-stressed silicon arsenic layer, a pressure within the reaction region is between 90 and 300 Torr.",
    "4. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein during the step of forming the tensile-stressed silicon arsenic layer, a carrier gas flow rate is between about 10 to about 40 standard liters per minute.",
    "5. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein during the step of supplying an arsenic source to the reactor, arsenic is provided in a non-reactive diluent.",
    "6. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein the step of forming the tensile-stressed silicon arsenic layer comprises epitaxially forming the tensile-stressed silicon arsenic layer on the silicon surface.",
    "7. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein the step of forming the tensile-stressed silicon arsenic layer comprises forming a layer comprising greater than or equal to 5 E+21 arsenic atoms/cubic centimeter.",
    "8. The method of forming a tensile-stressed silicon arsenic layer of claim 1, further comprising forming a structure comprising the tensile-stressed silicon arsenic layer.",
    "9. The method of forming a tensile-stressed silicon arsenic layer of claim 1, further comprising forming a device comprising the tensile-stressed silicon arsenic layer.",
    "10. The method of claim 1, wherein the tensile-stressed silicon arsenic layer forms a channel region of a transistor device."
  ],
  "description_excerpt": "The present disclosure generally relates to semiconductor structures and devices and to methods of forming the structures and devices. More particularly, the disclosure relates to structures and devices that include a silicon arsenic layer and to methods of forming the structures and devices.\n\nSemiconductor devices may include a tensile-stressed layer for a variety of reasons. For example, metal oxide semiconductor (MOS) devices may include a tensile-stressed layer, which forms part of a channel region of the devices. The tensile-stressed layer may exhibit higher carrier mobility - compared to a similar, non-stressed layer. As a result, devices formed with, for example, a tensile-stressed channel layer or region may exhibit faster switching speeds, better performance, and/or lower power consumption.\n\nMany semiconductor devices use silicon as a semiconducting material for a channel region within MOS devices. In these cases, a tensile stress in the silicon (e.g., a silicon layer) may be created by doping a silicon layer with carbon atoms, which are smaller and have a smaller lattice constant than silicon atoms. Because the carbon atoms are smaller than silicon atoms, when the carbon atoms form part of the substantially silicon crystal lattice, the crystal lattice becomes tensile stressed.\n\nAlthough doping silicon with carbon can create a tensile stress within a silicon lattice, adding carbon to the silicon lattice may reduce mobility of a carrier within the lattice structure (e.g., a channel region of a device).",
  "cpc": [
    "H10D 30/751",
    "H01L 21/02521",
    "H01L 21/02532",
    "H01L 21/02576",
    "H01L 21/0262",
    "H01L 21/67207",
    "H01L 29/1054",
    "H01L 29/267",
    "H10D 30/6211",
    "H10D 62/82",
    "H10P 10/00",
    "H10P 14/20",
    "H10P 14/24",
    "H10P 14/3402",
    "H10P 14/3411",
    "H10P 14/3442",
    "H10P 30/20",
    "H10P 72/0468"
  ],
  "ipc": [
    "H01L 29/267",
    "H01L 21/336",
    "H01L 29/10"
  ],
  "assignees": [
    "ASM IP Holding BV"
  ],
  "inventors": [
    "Keith Doran Weeks"
  ],
  "filing_date": "2013-09-04",
  "publication_date": "2016-04-26",
  "grant_date": "2016-04-26",
  "priority_date": "2012-09-26",
  "application_number": "US-201314018345-A",
  "family_id": "50338009",
  "cited_by_count": 499,
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