Inverse slope isolation and dual surface orientation integration

{
  "publication_number": "US7575968B2",
  "country": "US",
  "kind": "B2",
  "title": "Inverse slope isolation and dual surface orientation integration",
  "abstract": "A semiconductor process and apparatus provide a high performance CMOS devices (108, 109) with hybrid or dual substrates by etching a deposited oxide layer (62) using inverse slope isolation techniques to form tapered isolation regions (76) and expose underlying semiconductor layers (41, 42) in a bulk wafer structure prior to epitaxially growing the first and second substrates (84, 82) having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes (104) over a first substrate (84) that is formed by epitaxially growing (100) silicon and forming second gate electrodes (103) over a second substrate (82) that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.",
  "claims": [
    "1. A method for fabricating a semiconductor structure, comprising: bonding a first semiconductor layer having a first crystal orientation directly to a second semiconductor layer having a second crystal orientation that is different from the first crystal orientation; selectively removing a portion of the second semiconductor layer to expose the first semiconductor layer in a first predetermined region and to leave a remaining portion of the second semiconductor layer in a second predetermined region; forming a dielectric layer to completely cover the exposed first semiconductor layer and the remaining portion of the second semiconductor layer with a dielectric layer, where the dielectric layer has an upper surface and a bottom surface; forming first and second trench openings in the dielectric layer, wherein the first trench opening exposes a portion of the first semiconductor layer in the first predetermined region and the second trench opening exposes a portion of the second semiconductor layer in the second predetermined region, and wherein the first and second trench openings each have a first dimension at the upper surface and a second dimension at the bottom surface that is smaller than the first dimension; and filling at least part of the first and second trench openings by epitaxially growing semiconductor material from the exposed portion of the first semiconductor layer and the exposed portion of the second semiconductor layer so that the first trench opening is filled at least in part with a first epi layer that has a third crystal orientation that is the same as the first crystal orientation and so that the second trench opening is filled at least in part with a second epi layer that has a fourth crystal orientation that is the same as the second crystal orientation.",
    "2. The method of claim 1, further comprising performing a chemical mechanical polish step so that the first epi layer is substantially coplanar with the second epi layer.",
    "3. The method of claim 1, where selectively removing a portion of the second semiconductor layer comprises: forming a first mask layer over the second semiconductor layer having an opening over the first predetermined region; and using the first mask layer to etch the second semiconductor layer to expose the first semiconductor layer in the first predetermined region.",
    "4. The method of claim 1, where forming a dielectric layer comprises depositing an oxide layer to completely cover the exposed first semiconductor layer and the remaining portion of the second semiconductor layer.",
    "5. The method of claim 4, further comprising performing a chemical mechanical polish step to planarize the deposited oxide layer.",
    "6. The method of claim 1, wherein the first semiconductor layer comprises (100) p-type silicon and the second semiconductor layer comprises (110) n-type silicon.",
    "7. The method of claim 1, where the first epi layer is electrically isolated from the second epi layer by a shallow trench isolation region formed from the dielectric layer located between the first epi layer and the second epi layer.",
    "8. The method of claim 1, further comprising: forming a first gate electrode structure over the first epi layer; and forming a second gate electrode structure over the second epi layer.",
    "9. The method of claim 1, where filling at least part of the first and second trench openings comprises selectively growing epitaxial silicon layer so that the first trench opening is filled at least in part with a first epi silicon layer and so that the second trench opening is filled at least in part with a second epi silicon layer.",
    "10. A method for forming a semiconductor structure on a wafer, comprising: bonding a second semiconductor layer directly to at least part of a first semiconductor layer, where the second semiconductor layer has a crystal orientation that is different from the first crystal orientation of the first semiconductor layer; forming a first opening to expose a first region of the first semiconductor layer by removing a portion of the second semiconductor layer; forming a substantially planar insulator layer over the first and second semiconductor layers, where the substantially planar insulator layer has an upper surface and a bottom surface; forming first and second trench openings in the substantially planar insulator layer, wherein the first trench opening exposes a portion of the first semiconductor layer and the second trench opening exposes a portion of the second semiconductor layer, and wherein the first and second trench openings each have a first dimension at the upper surface and a second dimension at the bottom surface that is smaller than the first dimension; filling at least part of the first and second trench openings by epitaxially growing semiconductor material from the exposed portion of the first semiconductor layer and the exposed portion of the second semiconductor layer so that the first trench opening is filled at least in part with a first epi layer and so that the second trench opening is filled at least in part with a second epi layer; and planarizing the first and second epi layers so that the first epi layer is substantially coplanar with the second epi layer.",
    "11. The method of claim 10, where planarizing the first and second epi layers comprises performing a chemical mechanical polish step.",
    "12. The method of claim 10, wherein the first semiconductor layer comprises (100) p-type silicon and the second semiconductor layer comprises (110) n-type silicon.",
    "13. The method of claim 10, where forming a first opening comprises: forming a first mask layer over the second semiconductor layer having an opening over the first region; and using the first mask layer to etch the second semiconductor layer to expose the first semiconductor layer in the first region.",
    "14. The method of claim 10, where forming a substantially planar insulator layer comprises depositing an oxide layer to completely cover the exposed first semiconductor layer and the remaining portion of the second semiconductor layer.",
    "15. The method of claim 14, comprising performing a chemical mechanical polish step to planarize the deposited oxide layer.",
    "16. The method of claim 10, where forming first and second trench openings comprises selectively etching the substantially planar insulator layer to leave an electrical isolation region for isolating the first epi layer from the second epi layer.",
    "17. The method of claim 10, where filling at least part of the first and second trench openings comprises selectively growing epitaxial silicon layer so that the first trench opening is filled at least in part with a first epi silicon layer and so that the second trench opening is filled at least in part with a second epi silicon layer.",
    "18. A method for fabricating FET devices on dual substrates, comprising: providing a second semiconductor layer that is directly bonded to an underlying first semiconductor layer, where the second semiconductor layer has a different crystallographic orientation from the underlying first semiconductor layer; exposing the first semiconductor layer in a first area; forming a dielectric layer over the first and second semiconductor layers; applying an active etch process to selectively remove the dielectric layer to form first and second tapered trench openings in the dielectric layer, wherein the first tapered trench opening exposes a portion of the first semiconductor layer in a first predetermined region and the second tapered trench opening exposes a portion of the second semiconductor layer in a second predetermined region; selectively growing an epitaxial semiconductor material to fill at least part of the first and second tapered trench openings so that the first tapered trench opening is filled at least in part with a first epi layer and so that the second tapered trench opening is filled at least in part with a second epi layer, where the first and second epi layers have different crystallographic orientations; polishing the first and second epi layers so that the first epi layer is substantially coplanar with the second epi layer; and forming FET devices over the polished first and second epi layers.",
    "19. The method of claim 18, where forming FET devices comprises: forming at least a first insulator layer over the first and second epi layers; forming at least a first conductive gate layer over the first insulator layer; and selectively etching the first conductive gate layer to form FET gate electrodes.",
    "20. The method of claim 18, wherein the first semiconductor layer comprises (100) p-type silicon and the second semiconductor layer comprises (110) n-type silicon.",
    "21. The method of claim 18, further comprising preparing the exposed portion of the first semiconductor layer and the exposed portion of the second semiconductor layer by applying a wet clean process and an in-situ hydrogen bake process prior to selectively growing the epitaxial semiconductor material."
  ],
  "description_excerpt": "1. Field of the Invention\n\nThe present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to field effect transistors (FETs) fabricated on hybrid or dual substrates.\n\n2. Description of the Related Art\n\nTo address the difference in electron and hole mobility values for NMOS and PMOS transistor devices formed on semiconductor wafers having a single crystal orientation, CMOS devices are increasingly fabricated with hybrid substrates with different or dual surface orientations (DSO) using semiconductor-on-insulator (SOI) or bulk silicon wafer bonding to provide PMOS and NMOS devices with their own optimized crystal orientation. Prior attempts to integrate dual or hybrid substrates from a bonded SOI wafer have etched through the buried oxide layer to expose an underlying silicon layer which is used to epitaxially grow one of the crystal surface orientations, but have resulted in non-uniform silicon step/recess heights between the different crystal surfaces which require an additional chemical mechanical polish (CMP) step. An example is depicted in FIGS. 1-3 which show a device 10 having two crystal surface orientations - surface 7 having a first orientation and a semiconductor-on-insulator (SOI) layer 3 having a second orientation - separated by buried oxide layers 2 and isolation regions 4 and covered by nitride layers 6. As shown in FIG. 1, an epi silicon layer 7 (having the first orientation) is formed in an opening in the device 10, which itself was formed by etching through the SOI layer 3 and buried oxide layer 2 to expose a portion of the substrate 1.",
  "cpc": [
    "H10D 84/038",
    "H10D 84/0167"
  ],
  "ipc": [
    "H01L 21/8238"
  ],
  "assignees": [
    "Freescale Semiconductor Inc"
  ],
  "inventors": [
    "Mariam G. Sadaka",
    "Debby Eades",
    "Joe Mogab",
    "Bich-Yen Nguyen",
    "Melissa O. Zavala",
    "Gregory S. Spencer"
  ],
  "filing_date": "2007-04-30",
  "publication_date": "2009-08-18",
  "grant_date": "2009-08-18",
  "priority_date": "2007-04-30",
  "application_number": "US-74208107-A",
  "family_id": "39887469",
  "cited_by_count": 536,
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}