Patent · US10304940B1 · B1 · US

Gate cut and fin trim isolation for advanced integrated circuit structure fabrication

(11) Publication number

US10304940B1

(21) Application number

15/859,352

(22) Filing date

2017-12-30

(30) Priority date

2017-11-30

(43) Publication date

2019-05-28

(45) Date of grant

2019-05-28

(51) IPC

H01L 21/762; H01L 21/8234; H01L 27/088; H01L 29/06; H01L 29/66; H01L 29/78; H10N 97/00

(52) CPC

H10D Inorganic electric semiconductor devices: 64/017, 1/47, 1/474, 30/0212, 30/024, 30/0245, 30/611, 30/62, 30/6211, 30/6212, 30/6213, 30/6215, 30/6219, 30/791, 30/792, 30/794, 30/795, 30/797, 62/021, 62/115, 62/116, 62/151, 62/822, 62/834, 64/0112, 64/01354, 64/015, 64/021, 64/259, 64/513, 64/689, 84/0135, 84/0149, 84/0151, 84/0158, 84/0167, 84/017, 84/0172, 84/0177, 84/0181, 84/0186, 84/0188, 84/0193, 84/038, 84/834, 84/853, 84/856, 86/215, 89/10
H01L Semiconductor devices; electric solid state devices not otherwise provided for: 21/76232, 21/823431, 27/0886, 29/0653, 29/66545, 29/6656, 29/66818, 29/7843, 29/7848
H10B Electronic memory devices: 10/12
H10P Generic processes or apparatus for the manufacture or treatment of devices covered by class H10: 14/24, 14/27, 14/3411, 14/418, 14/69215, 14/69433, 50/282, 50/695, 50/73, 76/405, 76/4085
H10W Generic packages, interconnections, connectors or other constructional details of devices covered by class H10: 10/014, 10/0145, 10/17, 20/035, 20/037, 20/056, 20/063, 20/069, 20/0693, 20/071, 20/077, 20/081, 20/089, 20/098, 20/40, 20/42, 20/425, 20/43, 20/435, 20/4403, 20/4437, 20/48, 72/20, 72/30, 72/851, 74/15, 90/724, 90/734

(73) Assignee

Intel Corp

(72) Inventors

Tahir Ghani; Byron Ho; Michael L. Hattendorf; Christopher P. Auth

(54) Title

Gate cut and fin trim isolation for advanced integrated circuit structure fabrication

(57) Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.

Full text

View on Google Patents

Claims (20)

A method of fabricating an integrated circuit structure, the method comprising: forming a plurality of fins, individual ones of the plurality of fins along a first direction; forming a plurality of gate structures over the plurality of fins, individual ones of the gate structures along a second direction orthogonal to the first direction; forming a dielectric material structure between adjacent ones of the plurality of gate structures; removing a portion of a first of the plurality of gate structures to expose a first portion of each of the plurality of fins, and removing a portion of a second of the plurality of gate structures to expose a second portion of each of the plurality of fins; removing the exposed first portion of each of the plurality of fins but not removing the exposed second portion of each of the plurality of fins; and forming a first insulating structure in a location of the removed first portion of the plurality of fins, and forming a second insulating structure in a location of the removed portion of the second of the plurality of gate structures.
The method of claim 1, wherein removing the portions of the first and second of the plurality of gate structures comprises using a lithographic window wider than a width of each of the portions of the first and second of the plurality of gate structures.
The method of claim 1, wherein removing the exposed first portion of each of the plurality of fins comprises etching to a depth less than a height of the plurality of fins.
The method of claim 3, wherein the depth is greater than a depth of source or drain regions in the plurality of fins.
The method of claim 1, wherein the plurality of fins comprise silicon and are continuous with a portion of a silicon substrate.
An integrated circuit structure, comprising: a fin comprising silicon, the fin having a longest dimension along a first direction; an isolation structure over an upper portion of the fin, the isolation structure having a center along the first direction; a first gate structure over the upper portion of the fin, the first gate structure having a longest dimension along a second direction orthogonal to the first direction, wherein a center of the first gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction; a second gate structure over the upper portion of the fin, the second gate structure having a longest dimension along the second direction, wherein a center of the second gate structure is spaced apart from the center of the first gate structure by the pitch along the first direction; and a third gate structure over the upper portion of the fin opposite a side of the isolation structure from the first and second gate structures, the third gate structure having a longest dimension along the second direction, wherein a center of the third gate structure is spaced apart from the center of the isolation structure by the pitch along the first direction.
The integrated circuit structure of claim 6, wherein each of the first gate structure, the second gate structure and the third gate structure comprises a gate electrode on and between sidewalls of a high-k gate dielectric layer.
The integrated circuit structure of claim 7, wherein each of the first gate structure, the second gate structure and the third gate structure further comprises an insulating cap on the gate electrode and on and the sidewalls of the high-k gate dielectric layer.
The integrated circuit structure of claim 6, further comprising: a first epitaxial semiconductor region on the upper portion of the fin between the first gate structure and the isolation structure; a second epitaxial semiconductor region on the upper portion of the fin between the first gate structure and the second gate structure; and a third epitaxial semiconductor region on the upper portion of the fin between the third gate structure and the isolation structure.
The integrated circuit structure of claim 9, wherein the first, second and third epitaxial semiconductor regions comprise silicon and germanium.
The integrated circuit structure of claim 9, wherein the first, second and third epitaxial semiconductor regions comprise silicon.
An integrated circuit structure, comprising: a shallow trench isolation (STI) structure between a pair of semiconductor fins, the STI structure having a longest dimension along a first direction; an isolation structure on the STI structure, the isolation structure having a center along the first direction; a first gate structure on the STI structure, the first gate structure having a longest dimension along a second direction orthogonal to the first direction, wherein a center of the first gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction; a second gate structure on the STI structure, the second gate structure having a longest dimension along the second direction, wherein a center of the second gate structure is spaced apart from the center of the first gate structure by the pitch along the first direction; and a third gate structure on the STI structure opposite a side of the isolation structure from the first and second gate structures, the third gate structure having a longest dimension along the second direction, wherein a center of the third gate structure is spaced apart from the center of the isolation structure by the pitch along the first direction.
The integrated circuit structure of claim 12, wherein each of the first gate structure, the second gate structure and the third gate structure comprises a gate electrode on and between sidewalls of a high-k gate dielectric layer.
The integrated circuit structure of claim 13, wherein each of the first gate structure, the second gate structure and the third gate structure further comprises an insulating cap on the gate electrode and on and the sidewalls of the high-k gate dielectric layer.
The integrated circuit structure of claim 12, wherein the pair of semiconductor fins is a pair of silicon fins.
The integrated circuit structure of claim 12, wherein the STI structure comprises: a first insulating layer directly on sidewalls of lower fin portions of the pair of semiconductor fins, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen; a second insulating layer directly on the first insulating layer; and a dielectric fill material directly on and laterally adjacent to the second insulating layer.
The integrated circuit structure of claim 16, wherein the first insulating layer comprises the silicon and oxygen and has no other atomic species having an atomic concentration greater than 1E15 atoms per cubic centimeter.
The integrated circuit structure of claim 16, wherein the first insulating layer has a thickness in the range of 0.5-2 nanometers.
The integrated circuit structure of claim 16, wherein the second insulating layer has a thickness in the range of 2-5 nanometers.
The integrated circuit structure of claim 16, wherein the dielectric fill material comprises silicon and oxygen.

Description

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.

Variability in conventional and currently known fabrication processes may limit the possibility to further extend them into the 10 nanometer node or sub-10 nanometer node range. Consequently, fabrication of the functional components needed for future technology nodes may require the introduction of new methodologies or the integration of new technologies in current fabrication processes or in place of current fabrication processes.

FIG. 1A illustrates a cross-sectional view of a starting structure following deposition, but prior to patterning, of a hardmask material layer formed on an interlayer dielectric (ILD) layer.

FIG. 1B illustrates a cross-sectional view of the structure of FIG. 1A following patterning of the hardmask layer by pitch halving.

Citations (91)

US5563082A
US6159782A
US6413802B1
US6396108B1
US6472258B1
US20030057486A1
US6689650B2
US20030111686A1
US6610576B2
US7187046B2
US6770516B2
US20040195628A1
US20040048424A1
US20040075122A1
US20120252193A1
US8222680B2
US8580660B2
US20040108545A1
US6821834B2
US20040110331A1
US7214991B2
US8334181B1
US6764884B1
US6812119B1
US8592280B2
US20090302372A1
US20090017584A1
US7476578B1
US20120083107A1
US9230959B2
US8264032B2
US20110049613A1
US20130062669A1
US8466027B2
US20130320456A1
US9716037B2
US9048260B2
US20140191300A1
US8912606B2
US20130277746A1
US20150255598A1
US9029923B2
US9202922B2
US20150194529A1
US9054085B2
US9246001B2
US20140361383A1
US9252276B2
US20140374845A1
US20150137219A1
US9024355B2
US9443951B2
US20130320399A1
US20140065774A1
US20170047400A1
US9484447B2
US9859368B2
US20140001441A1
US20140001572A1
US20140027860A1
US9728464B2
US20140077305A1
US20140191323A1
US8896067B2
US20140227846A1
US8859372B2
US20160056156A1
US20170229342A1
US9318582B2
US20150263128A1
US10153344B2
US20180006117A1
US20160204229A1
US9768256B2
US20150303281A1
US9391173B2
US20160260801A1
US9368497B2
US20150348966A1
US9608061B2
US20160099181A1
US9496182B2
US9406775B1
US20180158927A1
US20180158841A1
US20180083116A1
US10170576B2
WO2017111868A1
WO2017171794A1
US20180053761A1
US20180158811A1

Record as JSON

{
  "publication_number": "US10304940B1",
  "country": "US",
  "kind": "B1",
  "title": "Gate cut and fin trim isolation for advanced integrated circuit structure fabrication",
  "abstract": "Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.",
  "claims": [
    "1. A method of fabricating an integrated circuit structure, the method comprising: forming a plurality of fins, individual ones of the plurality of fins along a first direction; forming a plurality of gate structures over the plurality of fins, individual ones of the gate structures along a second direction orthogonal to the first direction; forming a dielectric material structure between adjacent ones of the plurality of gate structures; removing a portion of a first of the plurality of gate structures to expose a first portion of each of the plurality of fins, and removing a portion of a second of the plurality of gate structures to expose a second portion of each of the plurality of fins; removing the exposed first portion of each of the plurality of fins but not removing the exposed second portion of each of the plurality of fins; and forming a first insulating structure in a location of the removed first portion of the plurality of fins, and forming a second insulating structure in a location of the removed portion of the second of the plurality of gate structures.",
    "2. The method of claim 1, wherein removing the portions of the first and second of the plurality of gate structures comprises using a lithographic window wider than a width of each of the portions of the first and second of the plurality of gate structures.",
    "3. The method of claim 1, wherein removing the exposed first portion of each of the plurality of fins comprises etching to a depth less than a height of the plurality of fins.",
    "4. The method of claim 3, wherein the depth is greater than a depth of source or drain regions in the plurality of fins.",
    "5. The method of claim 1, wherein the plurality of fins comprise silicon and are continuous with a portion of a silicon substrate.",
    "6. An integrated circuit structure, comprising: a fin comprising silicon, the fin having a longest dimension along a first direction; an isolation structure over an upper portion of the fin, the isolation structure having a center along the first direction; a first gate structure over the upper portion of the fin, the first gate structure having a longest dimension along a second direction orthogonal to the first direction, wherein a center of the first gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction; a second gate structure over the upper portion of the fin, the second gate structure having a longest dimension along the second direction, wherein a center of the second gate structure is spaced apart from the center of the first gate structure by the pitch along the first direction; and a third gate structure over the upper portion of the fin opposite a side of the isolation structure from the first and second gate structures, the third gate structure having a longest dimension along the second direction, wherein a center of the third gate structure is spaced apart from the center of the isolation structure by the pitch along the first direction.",
    "7. The integrated circuit structure of claim 6, wherein each of the first gate structure, the second gate structure and the third gate structure comprises a gate electrode on and between sidewalls of a high-k gate dielectric layer.",
    "8. The integrated circuit structure of claim 7, wherein each of the first gate structure, the second gate structure and the third gate structure further comprises an insulating cap on the gate electrode and on and the sidewalls of the high-k gate dielectric layer.",
    "9. The integrated circuit structure of claim 6, further comprising: a first epitaxial semiconductor region on the upper portion of the fin between the first gate structure and the isolation structure; a second epitaxial semiconductor region on the upper portion of the fin between the first gate structure and the second gate structure; and a third epitaxial semiconductor region on the upper portion of the fin between the third gate structure and the isolation structure.",
    "10. The integrated circuit structure of claim 9, wherein the first, second and third epitaxial semiconductor regions comprise silicon and germanium.",
    "11. The integrated circuit structure of claim 9, wherein the first, second and third epitaxial semiconductor regions comprise silicon.",
    "12. An integrated circuit structure, comprising: a shallow trench isolation (STI) structure between a pair of semiconductor fins, the STI structure having a longest dimension along a first direction; an isolation structure on the STI structure, the isolation structure having a center along the first direction; a first gate structure on the STI structure, the first gate structure having a longest dimension along a second direction orthogonal to the first direction, wherein a center of the first gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction; a second gate structure on the STI structure, the second gate structure having a longest dimension along the second direction, wherein a center of the second gate structure is spaced apart from the center of the first gate structure by the pitch along the first direction; and a third gate structure on the STI structure opposite a side of the isolation structure from the first and second gate structures, the third gate structure having a longest dimension along the second direction, wherein a center of the third gate structure is spaced apart from the center of the isolation structure by the pitch along the first direction.",
    "13. The integrated circuit structure of claim 12, wherein each of the first gate structure, the second gate structure and the third gate structure comprises a gate electrode on and between sidewalls of a high-k gate dielectric layer.",
    "14. The integrated circuit structure of claim 13, wherein each of the first gate structure, the second gate structure and the third gate structure further comprises an insulating cap on the gate electrode and on and the sidewalls of the high-k gate dielectric layer.",
    "15. The integrated circuit structure of claim 12, wherein the pair of semiconductor fins is a pair of silicon fins.",
    "16. The integrated circuit structure of claim 12, wherein the STI structure comprises: a first insulating layer directly on sidewalls of lower fin portions of the pair of semiconductor fins, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen; a second insulating layer directly on the first insulating layer; and a dielectric fill material directly on and laterally adjacent to the second insulating layer.",
    "17. The integrated circuit structure of claim 16, wherein the first insulating layer comprises the silicon and oxygen and has no other atomic species having an atomic concentration greater than 1E15 atoms per cubic centimeter.",
    "18. The integrated circuit structure of claim 16, wherein the first insulating layer has a thickness in the range of 0.5-2 nanometers.",
    "19. The integrated circuit structure of claim 16, wherein the second insulating layer has a thickness in the range of 2-5 nanometers.",
    "20. The integrated circuit structure of claim 16, wherein the dielectric fill material comprises silicon and oxygen."
  ],
  "description_excerpt": "Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures.\n\nFor the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.\n\nVariability in conventional and currently known fabrication processes may limit the possibility to further extend them into the 10 nanometer node or sub-10 nanometer node range. Consequently, fabrication of the functional components needed for future technology nodes may require the introduction of new methodologies or the integration of new technologies in current fabrication processes or in place of current fabrication processes.\n\nFIG. 1A illustrates a cross-sectional view of a starting structure following deposition, but prior to patterning, of a hardmask material layer formed on an interlayer dielectric (ILD) layer.\n\nFIG. 1B illustrates a cross-sectional view of the structure of FIG. 1A following patterning of the hardmask layer by pitch halving.",
  "cpc": [
    "H10D 64/017",
    "H01L 21/76232",
    "H01L 21/823431",
    "H01L 27/0886",
    "H01L 29/0653",
    "H01L 29/66545",
    "H01L 29/6656",
    "H01L 29/66818",
    "H01L 29/7843",
    "H01L 29/7848",
    "H10B 10/12",
    "H10D 1/47",
    "H10D 1/474",
    "H10D 30/0212",
    "H10D 30/024",
    "H10D 30/0245",
    "H10D 30/611",
    "H10D 30/62",
    "H10D 30/6211",
    "H10D 30/6212",
    "H10D 30/6213",
    "H10D 30/6215",
    "H10D 30/6219",
    "H10D 30/791",
    "H10D 30/792",
    "H10D 30/794",
    "H10D 30/795",
    "H10D 30/797",
    "H10D 62/021",
    "H10D 62/115",
    "H10D 62/116",
    "H10D 62/151",
    "H10D 62/822",
    "H10D 62/834",
    "H10D 64/0112",
    "H10D 64/01354",
    "H10D 64/015",
    "H10D 64/021",
    "H10D 64/259",
    "H10D 64/513",
    "H10D 64/689",
    "H10D 84/0135",
    "H10D 84/0149",
    "H10D 84/0151",
    "H10D 84/0158",
    "H10D 84/0167",
    "H10D 84/017",
    "H10D 84/0172",
    "H10D 84/0177",
    "H10D 84/0181",
    "H10D 84/0186",
    "H10D 84/0188",
    "H10D 84/0193",
    "H10D 84/038",
    "H10D 84/834",
    "H10D 84/853",
    "H10D 84/856",
    "H10D 86/215",
    "H10D 89/10",
    "H10P 14/24",
    "H10P 14/27",
    "H10P 14/3411",
    "H10P 14/418",
    "H10P 14/69215",
    "H10P 14/69433",
    "H10P 50/282",
    "H10P 50/695",
    "H10P 50/73",
    "H10P 76/405",
    "H10P 76/4085",
    "H10W 10/014",
    "H10W 10/0145",
    "H10W 10/17",
    "H10W 20/035",
    "H10W 20/037",
    "H10W 20/056",
    "H10W 20/063",
    "H10W 20/069",
    "H10W 20/0693",
    "H10W 20/071",
    "H10W 20/077",
    "H10W 20/081",
    "H10W 20/089",
    "H10W 20/098",
    "H10W 20/40",
    "H10W 20/42",
    "H10W 20/425",
    "H10W 20/43",
    "H10W 20/435",
    "H10W 20/4403",
    "H10W 20/4437",
    "H10W 20/48",
    "H10W 72/20",
    "H10W 72/30",
    "H10W 72/851",
    "H10W 74/15",
    "H10W 90/724",
    "H10W 90/734"
  ],
  "ipc": [
    "H01L 21/762",
    "H01L 21/8234",
    "H01L 27/088",
    "H01L 29/06",
    "H01L 29/66",
    "H01L 29/78",
    "H10N 97/00"
  ],
  "assignees": [
    "Intel Corp"
  ],
  "inventors": [
    "Tahir Ghani",
    "Byron Ho",
    "Michael L. Hattendorf",
    "Christopher P. Auth"
  ],
  "filing_date": "2017-12-30",
  "publication_date": "2019-05-28",
  "grant_date": "2019-05-28",
  "priority_date": "2017-11-30",
  "application_number": "US-201715859352-A",
  "family_id": "63963951",
  "cited_by_count": 13,
  "citations": [
    "US5563082A",
    "US6159782A",
    "US6413802B1",
    "US6396108B1",
    "US6472258B1",
    "US20030057486A1",
    "US6689650B2",
    "US20030111686A1",
    "US6610576B2",
    "US7187046B2",
    "US6770516B2",
    "US20040195628A1",
    "US20040048424A1",
    "US20040075122A1",
    "US20120252193A1",
    "US8222680B2",
    "US8580660B2",
    "US20040108545A1",
    "US6821834B2",
    "US20040110331A1",
    "US7214991B2",
    "US8334181B1",
    "US6764884B1",
    "US6812119B1",
    "US8592280B2",
    "US20090302372A1",
    "US20090017584A1",
    "US7476578B1",
    "US20120083107A1",
    "US9230959B2",
    "US8264032B2",
    "US20110049613A1",
    "US20130062669A1",
    "US8466027B2",
    "US20130320456A1",
    "US9716037B2",
    "US9048260B2",
    "US20140191300A1",
    "US8912606B2",
    "US20130277746A1",
    "US20150255598A1",
    "US9029923B2",
    "US9202922B2",
    "US20150194529A1",
    "US9054085B2",
    "US9246001B2",
    "US20140361383A1",
    "US9252276B2",
    "US20140374845A1",
    "US20150137219A1",
    "US9024355B2",
    "US9443951B2",
    "US20130320399A1",
    "US20140065774A1",
    "US20170047400A1",
    "US9484447B2",
    "US9859368B2",
    "US20140001441A1",
    "US20140001572A1",
    "US20140027860A1",
    "US9728464B2",
    "US20140077305A1",
    "US20140191323A1",
    "US8896067B2",
    "US20140227846A1",
    "US8859372B2",
    "US20160056156A1",
    "US20170229342A1",
    "US9318582B2",
    "US20150263128A1",
    "US10153344B2",
    "US20180006117A1",
    "US20160204229A1",
    "US9768256B2",
    "US20150303281A1",
    "US9391173B2",
    "US20160260801A1",
    "US9368497B2",
    "US20150348966A1",
    "US9608061B2",
    "US20160099181A1",
    "US9496182B2",
    "US9406775B1",
    "US20180158927A1",
    "US20180158841A1",
    "US20180083116A1",
    "US10170576B2",
    "WO2017111868A1",
    "WO2017171794A1",
    "US20180053761A1",
    "US20180158811A1"
  ]
}

Record 2,793 of 8,000 in Patents full text (MLC-0201). Request the full dataset.