Semiconductor device and method for fabricating the same

{
  "publication_number": "US2007173007A1",
  "country": "US",
  "kind": "A1",
  "title": "Semiconductor device and method for fabricating the same",
  "abstract": "The semiconductor device includes an active region, a recess channel region, a storage node junction region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate, wherein a lower part of sidewalls of the active region is recessed. The recess channel is formed in the semiconductor substrate under the active region, wherein the recess channel has a vertical channel region and a horizontal channel region. The storage node junction region is formed over the device isolation structure and the semiconductor substrate. The gate insulating film is formed over the active region including the recess channel region. The gate electrode is formed over the gate insulating film to fill up the recess channel region.",
  "claims": [
    "1. A semiconductor device comprising: a device isolation structure formed in a semiconductor substrate to define an active region, wherein a lower part of sidewalls of the active region is recessed; a recess channel region formed in the semiconductor substrate under the active region, the recess channel region having a vertical channel region and a horizontal channel region; a storage node junction region formed over the device isolation structure and the semiconductor substrate; a gate insulating film formed over the active region including the recess channel region; and a gate electrode formed over the gate insulating film to fill up the recess channel region.",
    "2. The semiconductor device according to claim 1, wherein a thickness of the storage node junction region over the device isolation structure is equal to or less than that of the storage node junction region over the semiconductor substrate.",
    "3. The semiconductor device according to claim 1, wherein the substrate disposed between the device isolation structure and the vertical channel region is recessed such that a thickness of a portion of the substrate proximate to the storage node junction region is equal to or greater than a minimum width between the vertical channel region and the device isolation structure.",
    "4. The semiconductor device according to claim 1, wherein in a longitudinal direction of the active region, a width of a lower part of the horizontal channel region is equal to or greater than a width of an upper part of the horizontal channel region closer in proximity to the storage node junction.",
    "5. The semiconductor device according to claim 1, wherein in a longitudinal direction of the active region, a shape of the horizontal channel region is elliptical or circular.",
    "6. A method for fabricating a semiconductor device comprising: (a) forming a pad insulating film over a semiconductor substrate; (b) etching a predetermined region of the pad insulating film and the semiconductor substrate to form a trench defining an active region, wherein a lower part of sidewalls of the active region is recessed; (c) forming a device isolation structure that fills the trench; (d) removing the pad insulating film after the device isolation structure has been formed to expose the semiconductor substrate; (e) etching the exposed semiconductor substrate using a recess gate mask as an etching mask to form a recess; (f) forming a gate insulating film on the exposed semiconductor substrate; (g) forming a gate conductive layer filling the; (h) forming a gate hard mask layer over the gate conductive layer; and (i) patterning the gate hard mask layer and the gate conductive layer using a gate mask as an etching mask to form a gate.",
    "7. The method according to claim 6, wherein step (b) includes: (b-1) forming a first hard mask layer over the pad insulating film; (b-2) etching a predetermined region of the first hard mask layer, the pad insulating film, and the semiconductor substrate to form a first trench defining an active region; (b-3) forming spacers on sidewalls of the first trench; (b-4) etching the semiconductor substrate exposed in the first trench using the first hard mask layer and the spacers as an etching mask to form a second trench; and (b-5) etching the semiconductor substrate exposed in the second trench to form a third trench including an undercut space where a predetermined thickness of the semiconductor substrate under a storage node junction region is removed.",
    "8. The method according to claim 7, wherein the first hard mask layer is selected from the group consisting of an oxide film, a nitride film, a polysilicon layer, and combinations thereof.",
    "9. The method according to claim 7, wherein the spacer is selected from the group consisting of an oxide film, a nitride film, a polysilicon layer and combinations thereof.",
    "10. The method according to claim 7, wherein the etching process for the third trench in step (b-5) is performed using an isotropic etching method.",
    "11. The method according to claim 7, further comprising removing the first hard mask layer and the spacers.",
    "12. The method according to claim 11, wherein the removing process for the first hard mask layer and the spacer is performed using a wet etching method.",
    "13. The method according to claim 6, wherein step (e) includes: (e-1) forming a buffer oxide film over the exposed semiconductor substrate; (e-2) forming a planarized second hard mask layer over the buffer oxide film; (e-3) forming a photoresist film pattern defining a recess gate region over the second hard mask layer; (e-4) etching the second hard mask layer, the buffer oxide film, and a predetermined thickness of the semiconductor device using the photoresist film pattern using an etching mask to form a recess; (e-5) removing the photoresist film pattern and the second hard mask layer; and (e-6) removing the buffer oxide film.",
    "14. The method according to claim 13, further comprising injecting impurity ions into the semiconductor substrate to form a well and channel ion implantation region in the semiconductor substrate disposed under the buffer oxide film.",
    "15. The method according to claim 13, wherein the second hard mask layer is selected from the group consisting of a nitride film, a polysilicon film, a amorphous Carbon film, a SiON film, and combinations thereof.",
    "16. The method according to claim 13, further comprising: forming recess sidewall spacers on sidewalls of the recess and the buffer oxide film; etching a predetermined thickness of the semiconductor substrate exposed at the bottom of the recess using the recess sidewall spacers as an etching mask; and removing the recess sidewall spacers.",
    "17. The method according to claim 16, wherein the recess sidewall spacer is a stacked structure comprising an oxide film and a nitride film.",
    "18. The method according to claim 16, wherein the etching process for the semiconductor substrate is performed using an isotropic etching method.",
    "19. The method according to claim 18, wherein in a longitudinal direction of the active region, a shape of a lower part of the recess is elliptical or circular.",
    "20. The method according to claim 16, wherein the removing process for the recess sidewall spacer is performed using a wet etching method."
  ],
  "description_excerpt": "The present invention relates to a memory device. More particularly, the present invention relates to a semiconductor device and a method for fabricating the same wherein a lower part of sidewalls of an active region where a storage node junction region is to be formed is etched, and a portion of the storage node junction region is formed over a device isolation structure to form a vertical SOI (Silicon-on-Insulator) channel region, thereby increasing write/read speed characteristics of the device and improving a refresh characteristic of the device. When a channel length of a cell transistor is decreased, an ion concentration of a cell channel region is generally increased in order to maintain a threshold voltage of the cell transistor. An electric field in source/drain regions of the cell transistor is enhanced to increase leakage current, which results in degradation of a refresh characteristic of a DRAM structure. Therefore, there is a need for semiconductor devices in which the refresh characteristic is improved.\n\nFIG. 1 is a simplified layout of a conventional semiconductor device, wherein reference numerals 1, 2, and 3 denote an active region, a recess gate region, and a gate region, respectively. Referring to FIG. 1, a width of the recess gate region 2 is less than that of the gate region 3 by a distance 2 D. A distance F is the distance between the neighboring gate regions 3. FIGS. 2 a through 2 g are simplified cross-sectional views illustrating a conventional method for fabricating a semiconductor device, wherein FIGS. 2 a (i) through 2 g (i) are cross-sectional views taken along the line I-I′ of FIG.",
  "cpc": [
    "H10D 64/018",
    "F16B 2/065",
    "F16L 21/065",
    "H10B 12/05",
    "H10B 12/053",
    "H10D 64/027",
    "H10D 64/513",
    "H10D 64/518",
    "H10D 86/01",
    "H10D 86/201"
  ],
  "ipc": [
    "H01L 21/336",
    "H01L 21/8238",
    "H10B 12/00",
    "H10B 99/00"
  ],
  "assignees": [
    "HYNIX SEMICONDUCTOR INC"
  ],
  "inventors": [
    "LEE SANG D",
    "JEONG JAE G"
  ],
  "filing_date": "2006-04-13",
  "publication_date": "2007-07-26",
  "priority_date": "2006-01-23",
  "application_number": "US-27963706-A",
  "family_id": "38102367",
  "citations": [
    "US2005133836A1",
    "US2006113590A1",
    "US2006237817A1",
    "US5982008A",
    "US6175140B1",
    "US6476444B1",
    "US6525360B2",
    "US6958518B2"
  ]
}