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Patent · US9117657B2 · B2 · US

Method for filling recesses using pre-treatment with hydrocarbon-containing gas

(11) Publication number
US9117657B2
(21) Application number
13/912,666
(22) Filing date
2013-06-07
(30) Priority date
2013-06-07
(43) Publication date
2015-08-25
(45) Date of grant
2015-08-25
(51) IPC
H10P 14/24; H10P 14/60
(52) CPC
  • H10P Generic processes or apparatus for the manufacture or treatment of devices covered by class H10: 14/68, 14/6336, 14/6338, 14/662, 14/6686, 14/6902, 14/6922, 90/12
  • C23C Coating metallic material; coating material with metallic material; surface treatment of metallic material by diffusion into the surface, by chemical conversion or substitution; coating by vacuum evaporation, by sputtering, by ion implantation or by chemical vapour deposition, in general: 16/02, 16/401
  • H01L Semiconductor devices; electric solid state devices not otherwise provided for: 21/0201, 21/02112
  • H10W Generic packages, interconnections, connectors or other constructional details of devices covered by class H10: 20/077, 20/098
(73) Assignee
ASM IP Holding BV
(72) Inventors
Akinori Nakano; Shintaro Ueda
(54) Title
Method for filling recesses using pre-treatment with hydrocarbon-containing gas
(57) Abstract

A method for filling recesses of a substrate with an insulation film includes: (i) exposing surfaces of the recesses of the substrate to a pre-deposition gas in a reactive state in a reaction space to treat the surfaces with reactive hydrocarbons generated from the pre-deposition gas without filling the recesses; and (ii) depositing a flowable insulation film using a process gas other than the pre-deposition gas on a surface of the substrate to fill the recesses treated in step (i) therewith by plasma reaction. The pre-deposition gas has at least one hydrocarbon unit in its molecule.

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Claims (17)

  1. A method for filling recesses of a substrate with an insulation film, comprising: (i) exposing surfaces of the recesses of the substrate to a pre-deposition gas in a reactive state in a reaction space to treat the surfaces with reactive hydrocarbons generated from the pre-deposition gas without filling the recesses, said pre-deposition gas being a hydrocarbon consisting of C and H but exclusive of methane, ethane, propane, ethylene, acetylene, and hexamethyldisilazane, said pre-deposition gas being excited by applying RF power to the reaction space under a pressure of about 100 Pa to about 1,200 Pa, whereby the surface of the recesses is rendered hydrophobic, having a water contact angle of more than 80° but less than 100°; and (ii) depositing a flowable insulation film using a process gas other than the pre-deposition gas on a surface of the substrate to fill the recesses treated in step (i) therewith by plasma reaction.
  2. The method according to claim 1, wherein step (i) continues until a film having a thickness of less than about 1.5 nm is formed on the surfaces, and thereafter is stopped.
  3. The method according to claim 1, wherein the pre-deposition gas contains a saturated hydrocarbon.
  4. The method according to claim 1, wherein during step (i), no oxidizing gas or halide gas is introduced to the reaction space.
  5. The method according to claim 1, wherein all the gas used in step (i) consists of the pre-deposition gas alone or a mixture of the pre-deposition gas and an inert gas.
  6. The method according to claim 1, wherein in step (i), the pre-deposition gas is excited by applying RF power to the reaction space to which the pre-deposition gas is introduced.
  7. The method according to claim 6, wherein the RF power is applied at a power of 0.35 W/cm 2 or less per area of the substrate.
  8. The method according to claim 1, wherein step (i) is conducted for a period of no less than about 30 seconds but no more than 300 seconds.
  9. The method according to claim 1, wherein step (ii) is conducted at a temperature of 50° C. or lower as the temperature of the substrate.
  10. The method according to claim 1, wherein steps (i) and (ii) are conducted continuously.
  11. The method according to claim 1, wherein the surfaces of the recesses prior to step (i) are hydrophilic.
  12. The method according to claim 11, wherein the surfaces of the recesses are constituted by silicon, GaAS, or quartz glass.
  13. The method according to claim 11, wherein the surfaces are further constituted by a wiring material.
  14. The method according to claim 1, wherein the flowable insulation film is a low-k film.
  15. The method according to claim 1, wherein the flowable film is constituted by silicon oxide.
  16. The method according to claim 1, wherein step (ii) is conducted by plasma-enhanced CVD.
  17. The method according to claim 1, wherein the pre-deposition gas excludes a silazane compound.

Description

1. Field of the Invention

The present invention generally relates to interlayer-insulating technology for semiconductor integrated circuits, and particularly relates to so-called flowable CVD methods for filling patterned recesses with an interlayer-insulating film where the distance between wiring lines is narrow.

2. Description of the Related Art

In recent years, semiconductor devices have made impressive progress and achieved high integration, high speed, and high capacity, which allow for micro-fabrication of wiring. As micro-fabrication of wiring progresses, signal delay and increase of power consumption becomes problematic due to the increase of line capacity of wiring in the multilayer wiring structure. To solve this problem and to reduce the line capacity of wiring, so-called low-k film whose dielectric constant is low has been developed as an insulation film between wires, in addition, as a wiring material, copper is mainly used fin the purpose of reducing resistivity of the wiring material itself and improving signal delay. A well-known method for forming multilayer wiring using a low-k film and copper is a damascene method.

In the damascene method, multilayer wiring is completed by first forming a low-k film, then forming grooves (trenches) or connecting holes (via holes) by lithographic exposure and etching, and finally embedding copper therein. This damascene method has been playing a leading role in the field of film multilayer wiring technology.

Citations (9)

  • US20010049202A1
  • US7888233B1
  • US20100221452A1
  • US7629277B2
  • US7582555B1
  • US7915139B1
  • US20070281496A1
  • US8187951B1
  • US7541297B2
Record as JSON
{
  "publication_number": "US9117657B2",
  "country": "US",
  "kind": "B2",
  "title": "Method for filling recesses using pre-treatment with hydrocarbon-containing gas",
  "abstract": "A method for filling recesses of a substrate with an insulation film includes: (i) exposing surfaces of the recesses of the substrate to a pre-deposition gas in a reactive state in a reaction space to treat the surfaces with reactive hydrocarbons generated from the pre-deposition gas without filling the recesses; and (ii) depositing a flowable insulation film using a process gas other than the pre-deposition gas on a surface of the substrate to fill the recesses treated in step (i) therewith by plasma reaction. The pre-deposition gas has at least one hydrocarbon unit in its molecule.",
  "claims": [
    "1. A method for filling recesses of a substrate with an insulation film, comprising: (i) exposing surfaces of the recesses of the substrate to a pre-deposition gas in a reactive state in a reaction space to treat the surfaces with reactive hydrocarbons generated from the pre-deposition gas without filling the recesses, said pre-deposition gas being a hydrocarbon consisting of C and H but exclusive of methane, ethane, propane, ethylene, acetylene, and hexamethyldisilazane, said pre-deposition gas being excited by applying RF power to the reaction space under a pressure of about 100 Pa to about 1,200 Pa, whereby the surface of the recesses is rendered hydrophobic, having a water contact angle of more than 80° but less than 100°; and (ii) depositing a flowable insulation film using a process gas other than the pre-deposition gas on a surface of the substrate to fill the recesses treated in step (i) therewith by plasma reaction.",
    "2. The method according to claim 1, wherein step (i) continues until a film having a thickness of less than about 1.5 nm is formed on the surfaces, and thereafter is stopped.",
    "3. The method according to claim 1, wherein the pre-deposition gas contains a saturated hydrocarbon.",
    "4. The method according to claim 1, wherein during step (i), no oxidizing gas or halide gas is introduced to the reaction space.",
    "5. The method according to claim 1, wherein all the gas used in step (i) consists of the pre-deposition gas alone or a mixture of the pre-deposition gas and an inert gas.",
    "6. The method according to claim 1, wherein in step (i), the pre-deposition gas is excited by applying RF power to the reaction space to which the pre-deposition gas is introduced.",
    "7. The method according to claim 6, wherein the RF power is applied at a power of 0.35 W/cm 2 or less per area of the substrate.",
    "8. The method according to claim 1, wherein step (i) is conducted for a period of no less than about 30 seconds but no more than 300 seconds.",
    "9. The method according to claim 1, wherein step (ii) is conducted at a temperature of 50° C. or lower as the temperature of the substrate.",
    "10. The method according to claim 1, wherein steps (i) and (ii) are conducted continuously.",
    "11. The method according to claim 1, wherein the surfaces of the recesses prior to step (i) are hydrophilic.",
    "12. The method according to claim 11, wherein the surfaces of the recesses are constituted by silicon, GaAS, or quartz glass.",
    "13. The method according to claim 11, wherein the surfaces are further constituted by a wiring material.",
    "14. The method according to claim 1, wherein the flowable insulation film is a low-k film.",
    "15. The method according to claim 1, wherein the flowable film is constituted by silicon oxide.",
    "16. The method according to claim 1, wherein step (ii) is conducted by plasma-enhanced CVD.",
    "17. The method according to claim 1, wherein the pre-deposition gas excludes a silazane compound."
  ],
  "description_excerpt": "1. Field of the Invention\n\nThe present invention generally relates to interlayer-insulating technology for semiconductor integrated circuits, and particularly relates to so-called flowable CVD methods for filling patterned recesses with an interlayer-insulating film where the distance between wiring lines is narrow.\n\n2. Description of the Related Art\n\nIn recent years, semiconductor devices have made impressive progress and achieved high integration, high speed, and high capacity, which allow for micro-fabrication of wiring. As micro-fabrication of wiring progresses, signal delay and increase of power consumption becomes problematic due to the increase of line capacity of wiring in the multilayer wiring structure. To solve this problem and to reduce the line capacity of wiring, so-called low-k film whose dielectric constant is low has been developed as an insulation film between wires, in addition, as a wiring material, copper is mainly used fin the purpose of reducing resistivity of the wiring material itself and improving signal delay. A well-known method for forming multilayer wiring using a low-k film and copper is a damascene method.\n\nIn the damascene method, multilayer wiring is completed by first forming a low-k film, then forming grooves (trenches) or connecting holes (via holes) by lithographic exposure and etching, and finally embedding copper therein. This damascene method has been playing a leading role in the field of film multilayer wiring technology.",
  "cpc": [
    "H10P 14/68",
    "C23C 16/02",
    "C23C 16/401",
    "H01L 21/0201",
    "H01L 21/02112",
    "H10P 14/6336",
    "H10P 14/6338",
    "H10P 14/662",
    "H10P 14/6686",
    "H10P 14/6902",
    "H10P 14/6922",
    "H10P 90/12",
    "H10W 20/077",
    "H10W 20/098"
  ],
  "ipc": [
    "H10P 14/24",
    "H10P 14/60"
  ],
  "assignees": [
    "ASM IP Holding BV"
  ],
  "inventors": [
    "Akinori Nakano",
    "Shintaro Ueda"
  ],
  "filing_date": "2013-06-07",
  "publication_date": "2015-08-25",
  "grant_date": "2015-08-25",
  "priority_date": "2013-06-07",
  "application_number": "US-201313912666-A",
  "family_id": "52005802",
  "cited_by_count": 521,
  "citations": [
    "US20010049202A1",
    "US7888233B1",
    "US20100221452A1",
    "US7629277B2",
    "US7582555B1",
    "US7915139B1",
    "US20070281496A1",
    "US8187951B1",
    "US7541297B2"
  ]
}

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