Nonvolatile semiconductor memory

{
  "publication_number": "US8779502B2",
  "country": "US",
  "kind": "B2",
  "title": "Nonvolatile semiconductor memory",
  "abstract": "According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer.",
  "claims": [
    "1. A nonvolatile semiconductor memory comprising: a semiconductor substrate; first to n-th (n is a natural number not less than 2) semiconductor layers which are stacked in order from the semiconductor substrate side in a first direction perpendicular to a surface of the semiconductor substrate and extend in a second direction parallel to the surface of the semiconductor substrate, and the semiconductor layers isolated each other and having a stair case pattern in a first end of the first to n-th semiconductor layers in the second direction; a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the first to n-th semiconductor layers, the common semiconductor layer having an upper surface higher than an upper surface of the n-th semiconductor layer; a first electrode connected to the common semiconductor layer; a second electrode connected to the first to n-th semiconductor layers in a second end of the first to n-th semiconductor layers in the second direction; first to n-th memory strings which are provided in corresponding to the first to n-th semiconductor layers, channels of the first to n-th memory strings being provided in the first to n-th semiconductor layers respectively; first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and select one of the first to n-th memory strings; and first to n-th impurity regions which are provided in the first to n-th semiconductor layers adjacent to the common semiconductor layer respectively, wherein the i-th layer select transistor (i is one of 1 to n) comprises first to n-th sub transistors which are provided in order from the first semiconductor layer between the first semiconductor layer and the upper surface of the common semiconductor layer, the i-th sub transistor of the i-th layer select transistor comprises the i-th impurity region as a channel which is provided in the i-th semiconductor layer, and the i-th impurity region has an impurity concentration higher than an impurity concentration of a channel of the sub transistor except the i-th sub transistor among the first to n-th sub transistors of the i-th layer select transistor.",
    "2. The memory of claim 1, wherein the first to n-th memory strings comprise memory cells connected in series in the second direction.",
    "3. The memory of claim 2, wherein each of the memory cells comprises a first insulating film, a charge storage layer, a second insulating film, and a control gate electrode stacked in a third direction perpendicular to the first and second directions.",
    "4. The memory of claim 3, wherein the control gate electrode extends to the first direction along a surface of the first to n-th semiconductor layers.",
    "5. The memory of claim 1, wherein each of first to n-th layer select transistors comprises a gate insulating film and a select gate electrode stacked in a third direction perpendicular to the first and second directions.",
    "6. The memory of claim 5, wherein the select gate electrode extends to the first direction along a surface of the first to n-th semiconductor layers.",
    "7. The memory of claim 1, wherein each of first to n-th layer select transistors comprises a first insulating film, a charge storage layer, a second insulating film and a select gate electrode stacked in a third direction perpendicular to the first and second directions.",
    "8. The memory of claim 7, wherein the select gate electrode extends to the first direction along a surface of the first to n-th semiconductor layers.",
    "9. The memory of claim 1, further comprising a select transistor which is provided between the second electrode and the first to n-th memory strings.",
    "10. The memory of claim 1, wherein the first to n-th semiconductor layers are electrically isolated by insulating layers.",
    "11. The memory of claim 1, wherein the first to n-th semiconductor layers are electrically isolated by air gaps.",
    "12. The memory of claim 1, wherein the first to n-th impurity regions include at least one of p-type impurities and n-type impurities.",
    "13. The memory of claim 1, wherein the first and second electrodes include one of tungsten and aluminum.",
    "14. The memory of claim 1, further comprising: impurity regions provided around the first and second electrodes.",
    "15. The memory of claim 3, wherein the first insulating film comprises a material selected from silicon oxide and silicon oxynitride, or the material including one of silicon nanoparticles and metal ions.",
    "16. The memory of claim 3, wherein the charge storage layer comprises a material selected from hafnium oxide and silicon nitride, or the material including one of silicon nanoparticles and metal ions.",
    "17. The memory of claim 3, wherein the second insulating film comprises a material selected from silicon oxide, aluminum oxide, lanthanum aluminum oxide, and lanthanum aluminum silicon oxide.",
    "18. The memory of claim 3, wherein the control gate electrode comprises a material selected from nickel silicide, tantalum nitride, tantalum carbide, and titanium nitride.",
    "19. The memory of claim 6, wherein the first to n-th semiconductor layers and the common semiconductor layer comprise a fin-type stacked structure.",
    "20. The memory of claim 1, further comprising an erase electrode which is provided on a surface of the first to n-th semiconductor layers, and to which a bias is applied in an erase operation.",
    "21. A method of manufacturing the memory of claim 1, the method comprising: forming the first to n-th semiconductor layers having the stair case pattern in the first end in the second direction; forming the first to n-th impurity regions in the first end of the first to n-th semiconductor layers by using an ion implantation; forming the common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the first to n-th semiconductors; forming a fin-type stacked structure by patterning the first to n-th semiconductor layers and the common semiconductor layer; and forming the first to n-th memory strings and the first to n-th layer select transistors on the fin-type stacked structure.",
    "22. The memory of claim 1, wherein the impurity concentration of the i-th impurity region is higher than an impurity concentration of the common semiconductor layer.",
    "23. The memory of claim 1, wherein the upper surface of the common semiconductor layer is flat."
  ],
  "cpc": [
    "H10D 30/6892",
    "H10B 41/20",
    "H10B 41/30",
    "H10B 41/35",
    "H10B 43/20",
    "H10B 43/30",
    "H10D 30/0411",
    "H10D 30/0413",
    "H10D 30/681",
    "H10D 30/69",
    "H10D 30/696",
    "H10D 64/035",
    "H10D 64/037"
  ],
  "assignees": [
    "SAKUMA KIWAMU",
    "KINOSHITA ATSUHIRO",
    "KIYOTOSHI MASAHIRO",
    "HAGISHIMA DAISUKE",
    "MURAOKA KOICHI",
    "TOSHIBA KK"
  ],
  "filing_date": "2011-12-12",
  "publication_date": "2014-07-15",
  "grant_date": "2014-07-15",
  "priority_date": "2009-06-12",
  "application_number": "US-201113316603-A",
  "family_id": "43308574",
  "citations": [
    "JP2004152893A",
    "JP2004349702A",
    "JP2006155750A",
    "JP2007266143A",
    "JP2008078404A",
    "JP2008166759A",
    "JP2009027136A",
    "JP2009124107A",
    "US2004235262A1",
    "US2008073635A1",
    "US2008157176A1",
    "US2009309152A1",
    "US2011272745A1",
    "US7777270B2",
    "US8008732B2"
  ]
}