Semiconductor device and method of manufacturing the same

{
  "publication_number": "US8710580B2",
  "country": "US",
  "kind": "B2",
  "title": "Semiconductor device and method of manufacturing the same",
  "abstract": "According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers.",
  "claims": [
    "1. A semiconductor device comprising: a semiconductor substrate; an insulating layer on the semiconductor substrate; first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of the insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other; a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof; and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers, wherein the layer select transistor comprises first to m-th gate electrodes (m=n+k, k is an even number) which are arranged in order from the first end of the second direction of the first to n-th semiconductor layers toward a second end of the second direction of the first to n-th semiconductor layers, and which extend in the first direction along side surfaces of the first to n-th semiconductor layers exposing in a third direction perpendicular to the first and second directions, and an i-th normally-on region (i is one of 1 to n) which sets channels adjacent to the i-th to (i+k)-th gate electrodes in the i-th semiconductor layer to normally-on channels, the normally-on channels which are not dependent on potentials of the i-th to (i+k)-th gate electrodes.",
    "2. The device of claim 1, wherein an off-potential is applied to the i-th to (i+k)-th gate electrodes to set channels adjacent to the i-th to (i+k)-th gate electrodes to off-channels, and an on-potential is applied to the other gate electrodes to set channels adjacent to the other gate electrodes to on-channels, when the i-th semiconductor layer is selected.",
    "3. The device of claim 1, wherein a size of the layer select transistor in the second direction is P×(n+k−1), where P is a pitch of the first to m-th gate electrodes, and n is 4 or more.",
    "4. The device of claim 1, wherein the first to n-th semiconductor layers are polycrystalline silicon layers, the i-th normally-on region includes arsenic, and a pitch of the first to m-th gate electrodes is 160 nm or less.",
    "5. The device of claim 1, wherein a low-resistance region with a resistance value lower than resistance values of the first to n-th semiconductor layers is provided in regions which are not covered by the first to m-th gate electrodes among side surfaces of the first to n-th semiconductor layers.",
    "6. The device of claim 1, wherein the first to n-th semiconductor layers are isolated from each other by an insulating layer or a cavity.",
    "7. The device of claim 1, further comprising: memory cells connected to the first to n-th semiconductor layers in the second end of the second direction thereof, wherein each of the memory cells is a cell transistor including a charge storage layer, the cell transistor having a threshold value changing based on a charge amount in the charge storage layer, and the first to n-th semiconductor layers are used as channels of the memory cells.",
    "8. The device of claim 1, further comprising: memory cells connected to the first to n-th semiconductor layers in the second end of the second direction thereof, wherein each of the memory cells is a resistance change element which has a resistance value changing based on a voltage or a current, and the first to n-th semiconductor layers are used as conductive lines to supply the voltage or the current to each of the memory cells.",
    "9. A semiconductor device comprising: a semiconductor substrate; an insulating layer on the semiconductor substrate; first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of the insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers having a stepped shape in a first end of the second direction thereof, the first to n-th semiconductor layers being insulated from each other; first to n-th diffusion prevention layers covering the first end of the first to n-th semiconductor layers respectively; a common semiconductor layer connected to the first to n-th semiconductor layers via the first to n-th diffusion prevention layers; and a common electrode connected to the common semiconductor layer; and a layer select transistor which uses the first to n-th semiconductor layers and the common semiconductor layer as channels and which selects one of the first to n-th semiconductor layers, wherein the layer select transistor comprises first to m-th gate electrodes (m=n+k, k is a natural number) which are arranged in order from the first end of the second direction of the first to n-th semiconductor layers toward a second end of the second direction of the first to n-th semiconductor layers, and which extend in the first direction along side surfaces of the first to n-th semiconductor layers and the common semiconductor layer exposing in a third direction perpendicular to the first and second directions, and an i-th normally-on region (i is one of 1 to n) which sets channels adjacent to the i-th to (i+k)-th gate electrodes in the i-th semiconductor layer to normally-on channels, the normally-on channels which are not dependent on potentials of the i-th to (i+k)-th gate electrodes, and the g-th gate electrode (g is one of 1 to n−1) is disposed between the g-th diffusion prevention layer and the (g+1)-th diffusion prevention layer, and the n-th to m-th gate electrodes are disposed closer to the second end of the first to n-th semiconductor layers than the n-th diffusion prevention layer.",
    "10. The device of claim 9, wherein an off-potential is applied to the to (i+k)-th gate electrodes to set channels adjacent to the i-th to (i+k)-th gate electrodes to off-channels, and an on-potential is applied to the other gate electrodes to set channels adjacent to the other gate electrodes to on-channels, when the i-th semiconductor layer is selected.",
    "11. The device of claim 9, wherein the diffusion prevention layer is an insulating layer with a thickness of 1 nm or less in the second direction.",
    "12. The device of claim 9, wherein the diffusion prevention layer is a conductive layer.",
    "13. The device of claim 9, wherein a size of the layer select transistor in the second direction is P×(n+k−1), where P is a pitch of the first to m-th gate electrodes, and n is 3 or more.",
    "14. The device of claim 9, wherein the first to n-th semiconductor layers are polycrystalline silicon layers, the i-th normally-on region includes arsenic, and a pitch of the first to m-th gate electrodes is 160 nm or less.",
    "15. The device of claim 9, wherein a low-resistance region with a resistance value lower than resistance values of the first to n-th semiconductor layers is provided in regions which are not covered by the first to m-th gate electrodes among side surfaces of the first to n-th semiconductor layers.",
    "16. The device of claim 9, wherein the first to n-th semiconductor layers are isolated from each other by an insulating layer or a cavity.",
    "17. The device of claim 9, further comprising: memory cells connected to the first to n-th semiconductor layers in the second end of the second direction thereof, wherein each of the memory cells is a cell transistor including a charge storage layer, the cell transistor having a threshold value changing based on a charge amount in the charge storage layer, and the first to n-th semiconductor layers are used as channels of the memory cells.",
    "18. The device of claim 9, further comprising: memory cells connected to the first to n-th semiconductor layers in the second end of the second direction thereof, wherein each of the memory cells is a resistance change element which has a resistance value changing based on a voltage or a current, and the first to n-th semiconductor layers are used as conductive lines to supply the voltage or the current to each of the memory cells."
  ],
  "cpc": [
    "H10D 30/6893",
    "H01L 27/1157",
    "H01L 27/11578",
    "H10B 41/20",
    "H10B 43/20",
    "H10B 43/35",
    "H10B 63/30",
    "H10B 63/84",
    "H10D 30/681",
    "H10D 30/69",
    "H10D 86/011",
    "H10D 86/215",
    "H10N 70/20",
    "H10P 30/20"
  ],
  "assignees": [
    "SAKUMA KIWAMU",
    "KUSAI HARUKA",
    "FUJII SHOSUKE",
    "ZHANG LI",
    "KIYOTOSHI MASAHIRO",
    "SHINGU MASAO",
    "TOSHIBA KK"
  ],
  "filing_date": "2012-11-29",
  "publication_date": "2014-04-29",
  "grant_date": "2014-04-29",
  "priority_date": "2011-11-29",
  "application_number": "US-201213689026-A",
  "family_id": "48465977",
  "citations": [
    "JP2006155750A",
    "US2008259687A1",
    "US2009309152A1",
    "US2012139030A1",
    "US7352018B2"
  ]
}