Self-aligned edge implanted cell to reduce leakage current and improve program speed in split-gate flash

{
  "publication_number": "US6180977B1",
  "country": "US",
  "kind": "B1",
  "title": "Self-aligned edge implanted cell to reduce leakage current and improve program speed in split-gate flash",
  "abstract": "A method is provided for fabricating a self-aligned edge implanted split-gate flash memory comprising a semiconductor substrate of a first conductivity type having separated first and second regions of a second conductivity type formed therein, the first and second regions defining a substrate channel region therebetween; a floating gate separated from a doped region in the substrate by an oxide layer; a control gate partially overlying and separated by an insulator from said floating gate; said floating gate having thin portions and thick portions; and said thin portions of said floating gate overlying twice doped regions in said semiconductor substrate to reduce surface leakage current and improve program speed of the memory cell.",
  "claims": [
    "1. A self-aligned edge implanted split-gate flash memory comprising: a semiconductor substrate of a first conductivity type having separated first and second regions of a second conductivity type formed therein, the first and second regions defining a substrate channel region therebetween; a floating gate separated from a doped region in the substrate by an oxide layer; a control gate partially overlying and separated by an oval shaped poly-oxide layer from said floating gate; said oval shaped poly-oxide layer having thin portions, including flat upper surface towards the edge of said oval shaped poly-oxide layer and thick portions towards the center of said oval shaped poly-oxide layer; and edge portions of said floating gate underlying said thin portions overlying twice doped regions in said semiconductor substrate.",
    "2. The self-aligned edge implanted split-gate flash memory of claim 1, wherein said floating gate and control gate comprise polycrystalline silicon.",
    "3. The self-aligned edge implanted split-gate flash memory of claim 1, wherein said thin and thick portions comprise oxidized polysilicon.",
    "4. The self-aligned edge implanted split-gate flash memory of claim 1, wherein said twice doped regions in said semiconductor substrate are aligned with edge of said floating gate."
  ],
  "cpc": [
    "H10D 30/0411",
    "H10D 30/6891"
  ],
  "assignees": [
    "TAIWAN SEMICONDUCTOR MFG"
  ],
  "filing_date": "1999-09-03",
  "publication_date": "2001-01-30",
  "grant_date": "2001-01-30",
  "priority_date": "1997-12-04",
  "application_number": "US-38963199-A",
  "family_id": "25530931",
  "citations": [
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  ]
}