Semiconductor device

{
  "publication_number": "US9450086B2",
  "country": "US",
  "kind": "B2",
  "title": "Semiconductor device",
  "abstract": "To enhance a semiconductor device. A semiconductor device has a plurality of p + -type semiconductor regions disposed between the mutually adjacent two gate trenches, in a cell region. The p + type semiconductor regions are disposed spaced apart from each other, in plan view, in a p-type body layer in a portion positioned between the mutually adjacent two gate trenches. Any of a p-type impurity concentration in each of the p + type semiconductor regions is higher than the p-type impurity concentration in the p-type body layer.",
  "claims": [
    "1. A semiconductor device, comprising: a semiconductor substrate; a first semiconductor layer of a first conductivity type, which is formed on a first main surface side of the semiconductor substrate; a second semiconductor layer of a second conductivity type, which is formed over the first semiconductor layer and which is different from the first conductivity type; a first trench portion which penetrates through the second semiconductor layer to thereby reach the first semiconductor layer; a second trench portion, in plan view, which is disposed spaced apart from the first trench portion, and which penetrates through the second semiconductor layer to thereby reach the first semiconductor layer; a first gate insulating film formed on an inner wall of the first trench portion; a second gate insulating film formed on an inner wall of the second trench portion; a first gate electrode formed so as to be embedded in the first trench portion over the first gate insulating film; a second gate electrode formed so as to be embedded in the second trench portion over the second gate insulating film; a first semiconductor region of the first conductivity type, which is in contact with the second semiconductor layer in a portion positioned between the first trench portion and the second trench portion and in contact with the first gate insulating film; a second semiconductor region of the first conductivity type, which is in contact with the second semiconductor layer in a portion positioned between the first trench portion and the second trench portion and in contact with the second gate insulating film; a third semiconductor region of the second conductivity type, which is formed in the second semiconductor layer in a portion positioned between the first trench portion and the second trench portion; and a fourth semiconductor region of the second conductivity type, the whole fourth semiconductor region is formed separated from the third semiconductor region in the second semiconductor layer and the whole fourth semiconductor region is formed in a portion of the second semiconductor layer positioned between the third semiconductor region and the second trench portion, wherein a first transistor is formed by the first semiconductor layer, the second semiconductor layer in a portion positioned between the first trench portion and the second trench portion, the first gate insulating film, the first gate electrode, and the first semiconductor region, wherein a second transistor is formed by the first semiconductor layer, the second semiconductor layer in a portion positioned between the first trench portion and the second trench portion, the second gate insulating film, the second gate electrode, and the second semiconductor region, and wherein both an impurity concentration of the second conductivity type in the third semiconductor region and an impurity concentration of the second conductivity type in the fourth semiconductor region are greater than an impurity concentration of the second conductivity type in the second semiconductor layer.",
    "2. The semiconductor device according to claim 1, wherein both the third semiconductor region and the fourth semiconductor region are in contact with the first semiconductor layer.",
    "3. The semiconductor device according to claim 1, comprising: a first electrode that is in contact with the second semiconductor layer in a portion positioned between the first trench portion and the second trench portion and with the first semiconductor region; and a second electrode in contact with the second semiconductor layer in a portion positioned between the first electrode and the second trench portion and with the second semiconductor region, wherein: the third semiconductor region is in contact with the first electrode; and the fourth semiconductor region is in contact with the second electrode.",
    "4. The semiconductor device according to claim 1, wherein: the third semiconductor region includes: a fifth semiconductor region of the second conductivity type, which is formed in the second semiconductor layer in a portion positioned between the first trench portion and the second trench portion; and a sixth semiconductor region of the second conductivity type, which is formed in the second semiconductor layer in a portion positioned over the fifth semiconductor region and which is in contact with the fifth semiconductor region, the fourth semiconductor region includes: a seventh semiconductor region of the second conductivity type, which is formed in the second semiconductor layer in a portion positioned between the third semiconductor region and the second trench portion; and an eighth semiconductor region of the second conductivity type, which is formed in the second semiconductor layer in a portion positioned over the seventh semiconductor region and which is in contact with the seventh semiconductor, and any of an impurity concentration of the second conductivity type in the fifth semiconductor region, an impurity concentration of the second conductivity type in the sixth semiconductor region, an impurity concentration of the second conductivity type in the seventh semiconductor region, and an impurity concentration of the second conductivity type in the eighth semiconductor region is higher than an impurity concentration of the second conductivity type in the second semiconductor layer.",
    "5. The semiconductor device according to claim 1, wherein: the third semiconductor region includes: a fifth semiconductor region of the second conductivity type, which is formed in the second semiconductor layer in a portion positioned between the first trench portion and the second trench portion; and a sixth semiconductor region of the second conductivity type, which is formed to be separated from the fifth semiconductor region in the second semiconductor layer in a portion positioned over the fifth semiconductor region, the fourth semiconductor region includes: a seventh semiconductor region of the second conductivity type, which is formed in the second semiconductor layer in a portion positioned between the third semiconductor region and the second trench portion; and an eighth semiconductor region of the second conductivity type, which is formed to be separated from the seventh semiconductor region in the second semiconductor layer in a portion positioned over the seventh semiconductor region, and any of an impurity concentration of the second conductivity type in the fifth semiconductor region, an impurity concentration of the second conductivity type in the sixth semiconductor region, an impurity concentration of the second conductivity type in the seventh semiconductor region, and an impurity concentration of the second conductivity type in the eighth semiconductor region is higher than an impurity concentration of the second conductivity type in the second semiconductor layer.",
    "6. The semiconductor device according to claim 1, wherein: in plan view, the third semiconductor region is formed in the second semiconductor layer in a portion positioned on a side closer to the first trench portion than a middle of the first trench portion and the second trench portion; and in plan view, the fourth semiconductor region is formed in the second semiconductor layer in a portion positioned on a side closer to the second trench portion than a middle of the first trench portion and the second trench portion.",
    "7. The semiconductor device according to claim 1, wherein the first semiconductor layer is formed on the first main surface side of the semiconductor substrate in a first region and a second region of the first main surface of the semiconductor substrate; wherein the second semiconductor layer is formed over the first semiconductor layer in the first region; wherein the semiconductor device further includes: in the second region, a third semiconductor layer of the second conductivity type that is formed over the first semiconductor layer; a third trench portion that penetrates through the third semiconductor layer to thereby reach the first semiconductor layer; a third gate insulating film formed on an inner wall of the third trench portion; a third gate electrode formed so as to be embedded in the third trench portion over the third gate insulating film; a ninth semiconductor region of the second conductivity type that is formed in the third semiconductor layer in a portion positioned in the periphery of the third trench portion; an interlayer insulating film formed so as to cover the third gate electrode and the third semiconductor layer; a fourth trench portion that penetrates through the interlayer insulating film to thereby reach the third gate electrode; and a third electrode formed inside the fourth trench portion and over the interlayer insulating film, and that is electrically coupled to the third gate electrode; wherein the third gate electrode is electrically coupled to the first gate electrode and the second gate electrode; and wherein an impurity concentration of the second conductivity type in the ninth semiconductor region is higher than an impurity concentration of the second conductivity type in the third semiconductor layer.",
    "8. The semiconductor device according to claim 7, wherein the second region is positioned on a side closer to an outer periphery of the semiconductor substrate than the first region.",
    "9. The semiconductor device according to claim 8, wherein the ninth semiconductor region is formed in the third semiconductor layer in a portion positioned on a side closer to an outer periphery of the semiconductor substrate than the third trench portion.",
    "10. The semiconductor device according to claim 8, wherein the first trench portion and the second trench portion extend respectively, in plan view, in a first direction; wherein the third trench portion and the fourth trench portion extend respectively, in plan view, in a second direction intersecting with the first direction; wherein the semiconductor device further includes: a fifth trench portion that extends, in plan view, in the second direction in the second region, and that penetrates through the third semiconductor layer in a portion positioned on a side closer to the first region than the third trench portion to thereby reach the first semiconductor layer; a fourth gate insulating film formed on an inner wall of the fifth trench portion; and a fourth gate electrode formed so as to be embedded in the fifth trench portion over the fourth gate insulating film; wherein the fourth gate electrode is electrically coupled to the first gate electrode and the second gate electrode; and wherein the ninth semiconductor region is formed in the third semiconductor layer in a portion positioned between the third trench portion and the fifth trench portion.",
    "11. The semiconductor device according to claim 10, wherein: the device has a tenth semiconductor region of the second conductivity type that is formed in the third semiconductor layer in a portion positioned between the ninth semiconductor region and the fifth trench portion; and an impurity concentration of the second conductivity type in the tenth semiconductor region is higher than an impurity concentration of the second conductivity type in the third semiconductor layer.",
    "12. The semiconductor device according to claim 1, wherein: the semiconductor substrate includes a semiconductor of the first conductivity type; and the semiconductor device further has a drain electrode that is electrically coupled to the semiconductor substrate.",
    "13. A semiconductor device, comprising: a semiconductor substrate; a first semiconductor layer of a first conductivity type that is formed, in a first region and a second region of a first main surface of the semiconductor substrate, on the first main surface side of the semiconductor substrate; a second semiconductor layer of a second conductivity type different from the first conductivity type, formed over the first semiconductor layer in the first region; a first trench portion that penetrates through the second semiconductor layer to thereby reach the first semiconductor layer; a first gate insulating film formed on an inner wall of the first trench portion; a first gate electrode formed so as to be embedded in the first trench portion over the first gate insulating film; a first semiconductor region of the first conductivity type that is in contact with the second semiconductor layer in a portion positioned in a periphery of the first trench portion and with the first gate insulating film; a third semiconductor layer of the second conductivity type that is formed in an upper layer portion of the first semiconductor layer in the second region; a second trench portion that penetrates through the third semiconductor layer to thereby reach the first semiconductor layer; a second gate insulating film formed on an inner wall of the second trench portion; a second gate electrode formed so as to be embedded in the second trench portion over the second gate insulating film; a second semiconductor region of the second conductivity type that is formed in the third semiconductor layer in a portion positioned in a periphery of the second trench portion; an interlayer insulating film formed so as to cover the second gate electrode and the third semiconductor layer; a third trench portion that penetrates through the interlayer insulating film to thereby reach the second gate electrode; and a first electrode that is formed inside the third trench portion and over the interlayer insulating film, and that is electrically coupled to the second gate electrode, wherein: a first transistor is formed by the first semiconductor layer, the second semiconductor layer in a portion positioned in a periphery of the first trench portion, the first gate insulating film, the first gate electrode and the first semiconductor region; the second gate electrode is electrically coupled to the first gate electrode; and an impurity concentration of the second conductivity type in the second semiconductor region is higher than an impurity concentration of the second conductivity type in the third semiconductor layer.",
    "14. The semiconductor device according to claim 13, wherein the second region is positioned on a side closer to a periphery of the semiconductor substrate than the first region.",
    "15. The semiconductor device according to claim 14, wherein the second semiconductor region is formed in the third semiconductor layer in a portion positioned on a side closer to an outer periphery of the semiconductor substrate than the second trench portion.",
    "16. The semiconductor device according to claim 14, wherein: the first trench portion extends, in plan view, in a first direction; the second trench portion and the third trench portion extend respectively, in plan view, in a second direction intersecting with the first direction; the semiconductor device furthermore has: a fourth trench portion that, in plan view, extends in the second direction, and that penetrates through the third semiconductor layer in a portion positioned on a side closer to the first region than the second trench portion to thereby reach the first semiconductor layer, in the second region; a third gate insulating film formed on an inner wall of the fourth trench portion; and a third gate electrode formed so as to be embed in the fourth trench portion over the third gate insulating film; the third gate electrode is electrically coupled to the first gate electrode; and the second semiconductor region is formed in the third semiconductor layer in a portion positioned between the second trench portion and the fourth trench portion.",
    "17. The semiconductor device according to claim 16, further comprising: a third semiconductor region of the second conductivity type that is formed in the third semiconductor layer in a portion positioned between the second semiconductor region and the fourth trench portion, wherein an impurity concentration of the second conductivity type in the third semiconductor region is higher than an impurity concentration of the second conductivity type of the third semiconductor layer.",
    "18. The semiconductor device according to claim 14, further comprising: a fourth semiconductor layer of the second conductivity type that is formed in an upper layer portion of the third semiconductor layer in a portion positioned on a side closer to an outer periphery of the semiconductor substrate than the second semiconductor region in the second region; and a fourth semiconductor region of the second conductivity type that is formed in the fourth semiconductor layer; wherein an impurity concentration of the second conductivity type in the fourth semiconductor region is higher than an impurity concentration of the second conductivity type in the fourth semiconductor layer.",
    "19. The semiconductor device according to claim 1, wherein the first trench portion and the second trench portion extend respectively, in plan view, in a first direction, wherein a distance between the third semiconductor region and the first trench portion is 0.5 to 1.5 μm in a second direction perpendicular to the first direction, and wherein a distance between the fourth semiconductor region and the second trench portion is 0.5 to 1.5 μm in a second direction perpendicular to the first direction."
  ],
  "cpc": [
    "H10D 30/668",
    "H01L 29/0696",
    "H01L 29/1095",
    "H01L 29/41766",
    "H01L 29/66727",
    "H01L 29/66734",
    "H01L 29/7813",
    "H10D 30/0295",
    "H10D 30/0297",
    "H10D 62/127",
    "H10D 62/393",
    "H10D 64/2527",
    "H10D 64/256"
  ],
  "assignees": [
    "RENESAS ELECTRONICS CORP"
  ],
  "filing_date": "2015-03-10",
  "publication_date": "2016-09-20",
  "grant_date": "2016-09-20",
  "priority_date": "2014-03-24",
  "application_number": "US-201514642793-A",
  "family_id": "54142899",
  "citations": [
    "JP2010534921A",
    "US2008246081A1",
    "US7910439B2",
    "US8859365B2",
    "US9219148B2"
  ]
}