High-level synthesis

{
  "id": "MLC-T-IND-002836",
  "term": "High-level synthesis",
  "field": "Industrial and trades",
  "definition": "An automated design process in electronic design automation (EDA) that translates an algorithmic description of a system into a register-transfer level (RTL) hardware description. It allows designers to work at a higher level of abstraction, reducing design time and complexity for integrated circuits. This approach is widely used in the development of System-on-Chip (SoC) designs.",
  "synonyms": [
    "HLS"
  ],
  "subject": "Electrical engineering",
  "translations": {
    "de": "High-Level Synthesis",
    "es": "síntesis de alto nivel",
    "fr": "synthèse de haut niveau"
  },
  "url": "https://mlchart.com/terminology/industrial/high-level-synthesis/"
}