Vertical digit lines for semiconductor devices

{
  "publication_number": "US12604464B2",
  "country": "US",
  "kind": "B2",
  "title": "Vertical digit lines for semiconductor devices",
  "abstract": "Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and vertically oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.",
  "claims": [
    "1. A memory device, comprising: an array of vertically stacked memory cells, the array having horizontally oriented access devices and access lines and vertically oriented digit lines, comprising: the horizontally oriented access devices having first source/drain regions and second source drain regions separated by channel regions, and gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures on a gate dielectric material; the horizontally oriented access lines separated from the channel region by the gate dielectric; horizontally oriented storage nodes electrically coupled to the second source/drain regions of the horizontally oriented access devices; and the vertically oriented digit lines electrically coupled to the first source/drain regions of the horizontally oriented access devices, wherein the vertically oriented digit lines are formed asymmetrically adjacent in electrical contact with the first source/drain regions; and wherein the array of vertically stacked memory cells is electrically coupled in one of an open digit line architecture or a folded digit line architecture.",
    "2. The memory device of claim 1, wherein the gates opposing the channel regions provide a subthreshold voltage (sub-Vt) slope in a range of approximately 45 to 100 millivolts per decade (mV/dec).",
    "3. The memory device of claim 1, wherein the vertically oriented digit lines comprise a highly phosphorus (P) doped (n+) poly-silicon germanium (SiGe) material.",
    "4. The memory device of claim 1, wherein the vertically oriented digit lines comprise a tungsten (W) material formed on a titanium/titanium nitride (TiN) material which forms a titanium silicide with the first source/drain regions of the horizontally oriented access devices.",
    "5. The memory device of claim 1, wherein the vertically oriented digit lines are formed symmetrically, in vertical alignment, in electrical contact with the first source/drain regions.",
    "6. A memory device, comprising: an array of vertically stacked memory cells, the array having horizontally oriented access devices and access lines and vertically oriented digit lines, comprising: the horizontally oriented access devices having first source/drain regions and second source drain regions separated by channel regions, and gates opposing the channel regions formed around the channel region as gate all around (GAA) structures on a gate dielectric material; the horizontally oriented access lines separated from the channel region by the gate dielectric; horizontally oriented storage nodes electrically coupled to the second source/drain regions of the horizontally oriented access devices: the vertically oriented digit lines electrically coupled to the first source/drain regions of the horizontally oriented access devices; and horizontally oriented capacitor cells having a bottom electrode formed in electrical contact with the second source/drain regions; and wherein the vertically oriented digit lines are formed asymmetrically adjacent in electrical contact with the first source/drain regions.",
    "7. The memory device of claim 6, wherein the channel region is deposited horizontally within a vertical stack.",
    "8. The memory device of claim 6, wherein the GAA structures include a conductive material having a top portion above a semiconductor material and a bottom material below the gate dielectric material.",
    "9. The memory device of claim 6, wherein the vertically oriented digit lines comprise a ruthenium (Ru) material.",
    "10. The memory device of claim 6, wherein the channel material comprises a high doped semiconductor material to form a conductive body contact to the horizontally oriented access devices.",
    "11. The memory device of claim 6, wherein a top electrode is separated from the bottom electrode by a cell dielectric.",
    "12. A memory device, comprising: an array of vertically stacked memory cells, the array having horizontally oriented access devices and access lines and vertically oriented digit lines, comprising: the horizontally oriented access devices having first source/drain regions and second source drain regions separated by channel regions, and gates opposing the channel regions formed around the channel region as gate all around (GAA) structures on a gate dielectric material; the horizontally oriented access lines separated from the channel region by the gate dielectric material; storage nodes electrically coupled to the second source/drain regions of the horizontally oriented access devices: the vertically oriented digit lines electrically coupled to the first source/drain regions of the horizontally oriented access devices; and capacitor cells having a first horizontally oriented electrode electrically coupled to the first source/drain regions and a second electrode separated from the first horizontally oriented electrode by a cell dielectric; and wherein the horizontally oriented access devices are formed in a vertical stack of materials formed on a silicon substrate, the vertical stack comprising repeating iterations of a first dielectric material, a second dielectric material, a semiconductor material, and a third dielectric material.",
    "13. The memory device of claim 12, wherein the horizontally oriented access lines opposing a channel region of the semiconductor material comprise a ruthenium (Ru) material.",
    "14. The memory device of claim 12, wherein the channel material comprises an insulator material.",
    "15. The memory device of claim 12, wherein the first dielectric material comprises an oxide material, the semiconductor material comprises a low doped, p-type (p−) polysilicon, and the second dielectric material and the third dielectric material comprise a silicon nitride (SiN) material, in repeating iterations vertically, to form the vertical stack.",
    "16. The memory device of claim 12, wherein a bottom electrode formed in electrical contact with the second source/drain regions."
  ],
  "description_excerpt": "This application is a Divisional of U.S. application Ser. No. 17/079,612, filed on Oct. 26, 2020, the contents of which are incorporated herein by reference.\n\nThe present disclosure relates generally to memory devices, and more particularly, to a vertical digit line for semiconductor devices.\n\nMemory is often implemented in electronic systems, such as computers, cell phones, hand-held devices, etc. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and may include random-access memory (RAM), dynamic random-access memory (DRAM), static random-access memory (SRAM), and synchronous dynamic random-access memory (SDRAM). Non-volatile memory may provide persistent data by retaining stored data when not powered and may include NAND flash memory, NOR flash memory, nitride read only memory (NROM), phase-change memory (e.g., phase-change random access memory), resistive memory (e.g., resistive random-access memory), cross-point memory, ferroelectric random-access memory (FeRAM), or the like.\n\nAs design rules shrink, less semiconductor space is available to fabricate memory, including DRAM arrays. A respective memory cell for DRAM may include an access device, e.g., transistor, having a first and a second source/drain regions separated by a channel region. A gate may oppose the channel region and be separated therefrom by a gate dielectric. An access line, such as a word line, is electrically connected to the gate of the DRAM cell. A DRAM cell can include a storage node, such as a capacitor cell, coupled by the access device to a digit line.",
  "cpc": [
    "H10B 12/36",
    "G11C 11/4023",
    "H01L 25/0657",
    "H01L 27/0688",
    "H10B 12/056"
  ],
  "ipc": [
    "H01L 27/06",
    "G11C 11/402",
    "H10B 12/00"
  ],
  "assignees": [
    "Micron Technology Inc"
  ],
  "inventors": [
    "Si-Woo Lee",
    "Sangmin Hwang"
  ],
  "filing_date": "2022-06-17",
  "publication_date": "2026-04-14",
  "grant_date": "2026-04-14",
  "priority_date": "2020-10-26",
  "application_number": "US-202217843662-A",
  "family_id": "81257128",
  "cited_by_count": 0,
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}