Mask data preparation method, semiconductor chip manufacturing method using the same, and computing device

{
  "publication_number": "US2026104634A1",
  "country": "US",
  "kind": "A1",
  "title": "Mask data preparation method, semiconductor chip manufacturing method using the same, and computing device",
  "abstract": "Provided is a mask data preparation method, including generating shot-level pattern data including a first layout and a second layout, in which the first layout and the second layout are located across a boundary line between a first shot-data region and a second shot-data region adjacent to the first shot-data region, generating a first correction layout and a first plurality of auxiliary patterns associated with the first layout based on the shot-level pattern data, generating a second correction layout and a second plurality of auxiliary patterns associated with the second layout based on the shot-level pattern data, generating corrected shot-level pattern data based on the first correction layout, the first plurality of auxiliary patterns, the second correction layout, and the second plurality of auxiliary patterns, extracting a first mask data based on the corrected shot-level pattern data, and extracting based on the corrected shot-level pattern data a second mask data.",
  "claims": [
    "1. A mask data preparation method, comprising: generating shot-level pattern data including a first layout and a second layout, the first layout and the second layout located across a boundary line between a first shot-data region and a second shot-data region adjacent to the first shot-data region; generating a first correction layout and a first plurality of auxiliary patterns associated with the first layout based on the shot-level pattern data; generating a second correction layout and a second plurality of auxiliary patterns associated with the second layout based on the shot-level pattern data; generating corrected shot-level pattern data based on the first correction layout, the first plurality of auxiliary patterns, the second correction layout, and the second plurality of auxiliary patterns; extracting a first mask data based on the corrected shot-level pattern data; and extracting a second mask data based on the corrected shot-level pattern data. 2. The method according to claim 1, wherein the generating the shot-level pattern data includes rearranging position information of the first layout and the second layout, based on a third reference point, using relative position information between position information of the first layout based on a first reference point and position information of the second layout based on a second reference point. 3. The method according to claim 2, wherein the third reference point corresponds to a center point of the first shot-data region or a center point of the second shot-data region. 4. The method according to claim 1, wherein the generating the corrected shot-level pattern data includes: based on the first correction layout, generating the first plurality of auxiliary patterns; and based on the second correction layout, generating the second plurality of auxiliary patterns. 5. The method according to claim 1, wherein the first plurality of auxiliary patterns overlap the first correction layout, and the second plurality of auxiliary patterns overlap the second correction layout. 6. The method according to claim 1, further comprising, based on at least one of the shot-level pattern data and the corrected shot-level pattern data, determining an overlapping region, wherein the determining the overlapping region includes: determining a first overlapping outline spaced apart from the boundary line toward the first shot-data region; determining a second overlapping outline spaced apart from the boundary line toward the second shot-data region; and determining an overlapping region defined by the first overlapping outline and the second overlapping outline, and the overlapping region includes a first partial overlapping region defined by the boundary line and the first overlapping outline, and a second partial overlapping region defined by the boundary line and the second overlapping outline. 7. The method according to claim 6, wherein the extracting the first mask data includes: extracting, as a part of the first correction layout, a first partial correction layout inside each of the first shot-data region and the second partial overlapping region; extracting, as a part of the second correction layout, a second partial correction layout inside each of the first shot-data region and the second partial overlapping region; extracting a first partial auxiliary pattern from the first plurality of auxiliary patterns in a remaining region excluding the second partial overlapping region in the second shot-data region; and extracting a second partial auxiliary pattern from the second plurality of auxiliary patterns in a remaining region excluding the second partial overlapping region in the second shot-data region. 8. The method according to claim 7, wherein the extracting the first mask data further includes rearranging position information of each of the first partial correction layout, the second partial correction layout, the first partial auxiliary pattern, and the second partial auxiliary pattern based on a fourth reference point associated with the first shot-data region. 9. The method according to claim 6, wherein the extracting the second mask data includes: extracting, as a part of the first correction layout, a third partial correction layout inside each of the second shot-data region and the first partial overlapping region; extracting, as a part of the second correction layout, a fourth partial correction layout inside each of the second shot-data region and the first partial overlapping region; extracting a third partial auxiliary pattern from the first plurality of auxiliary patterns in a remaining region excluding the first partial overlapping region in the first shot-data region; and extracting a fourth partial auxiliary pattern from the second plurality of auxiliary patterns in a remaining region excluding the first partial overlapping region in the first shot-data region. 10. The method according to claim 9, wherein extracting the second mask data further includes rearranging position information of each of the third partial correction layout, the fourth partial correction layout, the third partial auxiliary pattern, and the fourth partial auxiliary pattern based on a fifth reference point associated with the second shot-data region. 11. A semiconductor chip manufacturing method, comprising: generating shot-level pattern data including a first layout and a second layout, the first layout and the second layout on a boundary line between a first shot-data region and a second shot-data region adjacent to the first shot-data region; generating a first correction layout and a first plurality of auxiliary patterns associated with the first layout based on the shot-level pattern data; generating a second correction layout and a second plurality of auxiliary patterns associated with the second layout based on the shot-level pattern data; generating corrected shot-level pattern data based on the first correction layout, the first plurality of auxiliary patterns, the second correction layout, and the second plurality of auxiliary patterns; extracting a first mask data based on the corrected shot-level pattern data; extracting a second mask data based on the corrected shot-level pattern data; manufacturing a first mask based on the first mask data; manufacturing a second mask based on the second mask data; forming a first partial transfer pattern on a wafer using the first mask; and forming a second partial transfer pattern on the wafer using the second mask. 12. The method according to claim 11, wherein each of the first partial transfer pattern and the second partial transfer pattern are formed on the wafer in overlap with each other. 13. The method according to claim 11, wherein the corrected shot-level pattern data includes an overlapping region defined by a first overlapping outline and a second overlapping outline, the first overlapping outline is spaced apart from the boundary line toward the first shot-data region, the second overlapping outline is spaced apart from the boundary line toward the second shot-data region, and the overlapping region includes a first partial overlapping region defined by the boundary line and the first overlapping outline, and a second partial overlapping region defined by the boundary line and the second overlapping outline. 14. The method according to claim 13, wherein the first mask data includes: as a part of the first correction layout, a first partial correction layout included in the first shot-data region and the second partial overlapping region; as a part of the second correction layout, a second partial correction layout included in the first shot-data region and the second partial overlapping region; a first partial auxiliary pattern, from the first plurality of auxiliary patterns, in a remaining region excluding the second partial overlapping region in the second shot-data region; and a second partial auxiliary pattern, from the second plurality of auxiliary patterns, in a remaining region excluding the second partial overlapping region in the second shot-data region. 15. The method according to claim 14, wherein the first mask includes a first mask pattern and a second mask pattern, the first mask pattern includes a pattern corresponding to the first partial correction layout and the first partial auxiliary pattern, and the second mask pattern includes a pattern corresponding to the second partial correction layout and the second partial auxiliary pattern. 16. The method according to claim 13, wherein the second mask data further includes: as a part of the first correction layout, a third partial correction layout included in the second shot-data region and the first partial overlapping region; as a part of the second correction layout, a fourth partial correction layout included in the second shot-data region and the first partial overlapping region; a third partial auxiliary pattern, from the first plurality of auxiliary patterns, in a remaining region excluding the first partial overlapping region in the first shot-data region; and a fourth partial auxiliary pattern, from the second plurality of auxiliary patterns, in a remaining region excluding the first partial overlapping region in the first shot-data region. 17. The method according to claim 16, wherein the second mask includes a third mask pattern and a fourth mask pattern, the third mask pattern includes a pattern corresponding to the third partial correction layout and the third partial auxiliary pattern, and the fourth mask pattern includes a pattern corresponding to the fourth partial correction layout and the fourth partial auxiliary pattern. 18. The method according to claim 11, wherein the wafer includes a plurality of dies, the plurality of dies includes a first die and a second die that is different from the first die, the first die is associated with the first layout, and the second die is associated with the second layout. 19. The method according to claim 11, wherein the first partial transfer pattern and the second partial transfer pattern are formed using High-NA EUV equipment. 20. A computing device that performs mask data preparation, comprising: a non-transitory memory configured to store at least one instruction; and a processor including a plurality of processing cores, wherein the processor is configured to execute the at least one instruction to: generate shot-level pattern data including a first layout and a second layout, the first layout and the second layout located across a boundary line between a first shot-data region and a second shot-data region adjacent to the first shot-data region; generate a first correction layout and a first plurality of auxiliary patterns associated with the first layout based on the shot-level pattern data; generate a second correction layout and a second plurality of auxiliary patterns associated with the second layout based on the shot-level pattern data; generate corrected shot-level pattern data based on the first correction layout, the first plurality of auxiliary patterns, the second correction layout, and the second plurality of auxiliary patterns; extract a first mask data based on the corrected shot-level pattern data; and extract a second mask data based on the corrected shot-level pattern data."
  ],
  "description_excerpt": "The present disclosure relates to mask data preparation methods, semiconductor chip manufacturing methods using the same, and computing devices.\n\nIn general, circuit patterns are formed on wafers through a photolithography process and a subsequent etching process in the manufacturing process of semiconductor devices. At this time, each circuit pattern is transferred onto the wafer in the photolithography process using a mask according to a pre-designed layout. The circuit patterns formed across a plurality of shot regions on the wafer may be difficult to transfer accurately due to optical proximity effect (OPE). The optical proximity effect may cause pattern distortions at boundaries between the shot regions, and the more minute the spacing between adjacent patterns, the more pronounced the effect may be.\n\nIn particular, pattern errors due to optical proximity effect are likely to occur at the boundaries of the shot regions, and these errors may cause problems that make it difficult to secure additional process margins. Accordingly, for the pattern located at the boundary of the shot region, an appropriate solution is required to minimize or reduce pattern errors due to the optical proximity effect.\n\nIn order to solve or improve upon one or more problems (e.g., the problems described above and/or other problems not explicitly described herein), the present disclosure provides mask data preparation methods, semiconductor chip manufacturing methods using the same, and computing devices.",
  "cpc": [
    "G03F 1/22",
    "G03F 7/2026",
    "G03F 7/70033",
    "G03F 7/70433"
  ],
  "ipc": [
    "G03F 1/22",
    "G03F 7/00",
    "G03F 7/20"
  ],
  "assignees": [
    "Samsung Electronics Co Ltd"
  ],
  "inventors": [
    "Hyunjae Lee",
    "Yun-Ju Han"
  ],
  "filing_date": "2025-04-04",
  "publication_date": "2026-04-16",
  "priority_date": "2024-10-15",
  "application_number": "US-202519170131-A",
  "family_id": "99411405",
  "cited_by_count": 0
}