MLchartDataset catalogue

Place and route

Term · Semiconductors · MLC-T-SEM-000252

A two-stage process in the physical design of integrated circuits that transforms a logical netlist into a geometric layout. The placement stage determines the optimal locations for all standard cells and logic blocks on the chip area. The routing stage then creates the metal interconnects (wires) to connect the pins of these placed components according to the netlist specifications.

Table 1. Record
IdentifierMLC-T-SEM-000252
FieldSemiconductors
SubjectDesign, EDA & Devices
AbbreviationP&R
Record as JSON 
{
  "id": "MLC-T-SEM-000252",
  "term": "Place and route",
  "field": "Semiconductors",
  "definition": "A two-stage process in the physical design of integrated circuits that transforms a logical netlist into a geometric layout. The placement stage determines the optimal locations for all standard cells and logic blocks on the chip area. The routing stage then creates the metal interconnects (wires) to connect the pins of these placed components according to the netlist specifications.",
  "abbreviation": "P&R",
  "subject": "Design, EDA & Devices",
  "url": "https://mlchart.com/terminology/semiconductors/place-and-route/"
}

Record 261 of 390 in Semiconductors terminology (MLC-0108). Request the full dataset.