Vertical field-effect transistor with uniform bottom spacer

{
  "publication_number": "US10229985B1",
  "country": "US",
  "kind": "B1",
  "title": "Vertical field-effect transistor with uniform bottom spacer",
  "abstract": "A method of forming a semiconductor structure includes patterning two or more fins over a top surface of a bottom source/drain layer, the bottom source/drain layer disposed over a substrate. The method also includes forming bottom spacers disposed over the top surface of the bottom source/drain layer between the two or more fins, the bottom spacers having a uniform height on sidewalls of the two or more fins. The bottom spacers comprise dielectric regions disposed adjacent the sidewalls of the two or more fins and at least partially filling divots in the bottom source/drain regions, and liner regions disposed adjacent the dielectric regions. The two or more fins comprise channels for a vertical field-effect transistor (VFET) device.",
  "claims": [
    "1. A method of forming a semiconductor structure, comprising: patterning two or more fins over a top surface of a bottom source/drain layer, the bottom source/drain layer disposed over a substrate; and forming bottom spacers disposed over the top surface of the bottom source/drain layer between the two or more fins, the bottom spacers having a uniform height on sidewalls of the two or more fins; wherein the bottom spacers comprise: dielectric regions disposed adjacent the sidewalls of the two or more fins and at least partially filling divots in the bottom source/drain regions; and liner regions disposed adjacent the dielectric regions; and wherein the two or more fins comprise channels for a vertical field-effect transistor (VFET) device.",
    "2. The method of claim 1, wherein the dielectric regions of the bottom spacers comprise a low-k dielectric and the liner regions disposed adjacent the dielectric regions comprises a nitride liner.",
    "3. The method of claim 1, wherein patterning the two or more fins comprises: depositing a bottom source/drain material over the substrate to form the bottom source/drain layer; depositing a layer of fin material over the bottom/source drain layer; patterning a hard mask over a top surface of the fin material; and removing portions of the fin material exposed by the hard mask to pattern the two or more fins.",
    "4. The method of claim 3, wherein: the substrate comprises bulk silicon; the bottom/source drain layer comprises at least one of doped silicon and doped silicon germanium; the two or more fins comprise undoped silicon; and the hard mask comprises at least one of a nitride and an oxide-nitride bilayer.",
    "5. The method of claim 1, wherein forming the bottom spacers comprises: depositing a liner over the two or more fins and exposed portions of a top surface of the bottom source/drain layer; depositing an oxide over the liner; and performing chemical mechanical planarization of the oxide stopping on a top surface of the liner formed over the two or more fins.",
    "6. The method of claim 5, wherein depositing the liner comprises depositing liner material using a conformal deposition process and wherein the liner material comprises at least one of silicon nitride and silicon carbonitride.",
    "7. The method of claim 5, wherein forming the bottom spacers further comprises etching portions of the liner such that a height of a first portion of the liner surrounding a first sidewall of a given one of the two or more fins is different than a height of a second portion of the liner surrounding at least one of: a second sidewall of the given fin; and one or more sidewalls of at least one other one of the two or more fins.",
    "8. The method of claim 7, wherein etching portions of the liner comprises utilizing a reactive-ion etching process.",
    "9. The method of claim 7, wherein remaining portions of the liner form the liner regions of the bottom spacers.",
    "10. The method of claim 7, wherein forming the bottom spacers further comprises: etching a portion of the oxide; over-etching remaining portions of the liner, wherein over-etching the remaining portions of the liner forms: the divots in the bottom source/drain layer; and laterally undercut portions of the liner formed over a top surface of the bottom source/drain layer beneath remaining portions of the oxide; and removing the remaining portions of the oxide.",
    "11. The method of claim 10, wherein forming the bottom spacers further comprises: filling a dielectric material over the two or more fins to fill: (i) the divots in the bottom source/drain layer; and (ii) regions exposed by laterally undercutting the liner; and etching the dielectric material to form the dielectric regions of the bottom spacers.",
    "12. The method of claim 1, further comprising forming a dielectric layer on sidewalls of the two or more fins and over top surfaces of the bottom spacers, wherein a height of the dielectric layer is below top surfaces of the two or more fins.",
    "13. The method of claim 12, further comprising forming a work function metal layer over the dielectric layer.",
    "14. The method of claim 12, further comprising forming gates over the dielectric layer surrounding the two or more fins.",
    "15. The method of claim 14, further comprising forming top spacers over the gates and the dielectric layer, the top spacers having top surfaces with heights matching top surfaces of the two or more fins.",
    "16. The method of claim 15, further comprising: depositing an interlayer dielectric layer over the top surfaces of the top spacers; removing hard masks disposed over the two or more fins; and forming top source/drain epitaxial layers over the top surfaces of the two or more fins in regions exposed by removal of the hard masks.",
    "17. A semiconductor structure, comprising: a substrate; bottom source/drain regions disposed over the substrate; two or more fins disposed over a top surface of the bottom source/drain regions; and bottom spacers disposed over the top surface of the bottom source/drain layer between the two or more fins, the bottom spacers having a uniform height on sidewalls of the two or more fins; wherein the bottom spacers comprise: dielectric regions disposed adjacent the sidewalls of the two or more fins and at least partially filling divots in the bottom source/drain regions; and liner regions disposed adjacent the dielectric regions; and wherein the two or more fins comprise channels for a vertical field-effect transistor (VFET) device.",
    "18. The semiconductor structure of claim 17, further comprising: a dielectric layer disposed on sidewalls of the two or more fins and over top surfaces of the bottom spacers; gates disposed over the dielectric layer surrounding the two or more fins; top spacers disposed over the gates and the dielectric layer, the top spacers having top surfaces with heights matching top surfaces of the two or more fins; an interlayer dielectric layer disposed over the top surfaces of the top spacers; and top source/drain epitaxial layers disposed over the top surfaces of the two or more fins.",
    "19. An integrated circuit comprising: a vertical field-effect transistor (VFET) device comprising: a substrate; bottom source/drain regions disposed over the substrate; two or more fins disposed over a top surface of the bottom source/drain regions, the two or more fins comprising channels for the VFET device; and bottom spacers disposed over the top surface of the bottom source/drain layer between the two or more fins, the bottom spacers having a uniform height on sidewalls of the two or more fins; wherein the bottom spacers comprise: dielectric regions disposed adjacent the sidewalls of the two or more fins and at least partially filling divots in the bottom source/drain regions; and liner regions disposed adjacent the dielectric regions.",
    "20. The integrated circuit of claim 19, wherein the VFET device further comprises: a dielectric layer disposed on sidewalls of the two or more fins and over top surfaces of the bottom spacers; gates disposed over the dielectric layer surrounding the two or more fins; top spacers disposed over the gates and the dielectric layer, the top spacers having top surfaces with heights matching top surfaces of the two or more fins; an interlayer dielectric layer disposed over the top surfaces of the top spacers; and top source/drain epitaxial layers disposed over the top surfaces of the two or more fins."
  ],
  "description_excerpt": "The present application relates to semiconductors, and more specifically, to techniques for forming semiconductor structures. Semiconductor structures include complementary metal-oxide-semiconductor (CMOS) structures. CMOS technology may be used for constructing integrated circuits, and finds uses in microprocessors, microcontrollers, static random-access memory (RAM) and other digital logic circuits. CMOS structures may use complementary and symmetrical pairs of p-type and n-type metal-oxide-semiconductor field effect transistors (MOSFETs) for logic functions.\n\nAs demands to reduce the size of transistor devices continue, new designs and fabrication techniques to achieve reduced device footprints are needed. Vertical-type transistors, such as vertical field-effect transistors (vertical FETs or VFETs) are an example of such a new design. When forming vertical FETs, spacers are provided between and around vertical structures.\n\nEmbodiments of the invention provide techniques for forming VFETs with uniform bottom spacers.\n\nFor example, in one embodiment a method of forming a semiconductor structure comprises patterning two or more fins over a top surface of a bottom source/drain layer, the bottom source/drain layer disposed over a substrate. The method also comprises forming bottom spacers disposed over the top surface of the bottom source/drain layer between the two or more fins, the bottom spacers having a uniform height on sidewalls of the two or more fins.",
  "cpc": [
    "H01L 29/66553",
    "H01L 21/31053",
    "H01L 21/31111",
    "H01L 21/31116",
    "H01L 29/0653",
    "H01L 29/6653",
    "H01L 29/6656",
    "H01L 29/66666",
    "H01L 29/7827",
    "H10D 30/025",
    "H10D 30/63",
    "H10D 62/116",
    "H10D 64/015",
    "H10D 64/018",
    "H10D 64/021",
    "H10P 50/283",
    "H10P 95/062"
  ],
  "ipc": [
    "H01L 21/3105",
    "H01L 21/311",
    "H10D 62/10"
  ],
  "assignees": [
    "International Business Machines Corp"
  ],
  "inventors": [
    "Juntao Li",
    "Kangguo Cheng",
    "Peng Xu",
    "Heng Wu"
  ],
  "filing_date": "2017-12-04",
  "publication_date": "2019-03-12",
  "grant_date": "2019-03-12",
  "priority_date": "2017-12-04",
  "application_number": "US-201715830665-A",
  "family_id": "65633152",
  "cited_by_count": 287,
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}