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Patent · US2015287942A1 · A1 · US

Forming pn junction contacts by different dielectrics

(11) Publication number
US2015287942A1
(21) Application number
14/618,618
(22) Filing date
2015-02-10
(30) Priority date
2014-04-07
(43) Publication date
2015-10-08
(51) IPC
H10D 62/10; H10K 99/00; H01L 21/02
(52) CPC
  • H01L Semiconductor devices; electric solid state devices not otherwise provided for: 51/0541, 51/002, 51/0048, 51/0525, 51/0558, 51/105
  • H10D Inorganic electric semiconductor devices: 62/118, 62/119, 62/121
  • H10K Organic electric solid-state devices: 10/46, 10/464, 10/468, 10/472, 10/484, 10/84, 2102/00, 71/30, 85/221
  • H10P Generic processes or apparatus for the manufacture or treatment of devices covered by class H10: 14/3464
  • H10W Generic packages, interconnections, connectors or other constructional details of devices covered by class H10: 20/0554
(73) Assignee
International Business Machines Corp
(72) Inventors
Qing Cao; Shu-Jen Han
(54) Title
Forming pn junction contacts by different dielectrics
(57) Abstract

A carbon nanotube transistor and method of manufacturing a carbon nanotube transistor is disclosed. The carbon nanotube transistor includes a carbon nanotube on a substrate, a gate electrode deposited on the carbon nanotube, and at least one of a source electrode and a drain electrode deposited on the carbon nanotube and separated from the gate electrode by a space region. The carbon nanotube is doped at the gate electrode an in the space region to form a p-n junction.

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Claims (1)

  1. A carbon nanotube transistor, comprising: one or more carbon nanotubes on a substrate; a gate structure including a gate electrode deposited on the carbon nanotube; and at least one of a source electrode and a drain electrode deposited on the one or more carbon nanotube and separated from the gate electrode by a space region, wherein the carbon nanotube is doped at the gate electrode and in the space region to form a p-n junction. 2. The carbon nanotube transistor of claim 1 further comprising a first dielectric configured to provide a first doping to the carbon nanotube at the gate electrode and a second dielectric configured to provide a second doping to the carbon nanotube in the space region to form the p-n junction. 3. The carbon nanotube transistor of claim 2, wherein the first doping is one of an n-type doping and a p-type doping and the second doping is the other of the n-type doping and the p-type doping. 4. The carbon nanotube transistor of claim 3, wherein the first dielectric is one of AlON and HfO 2 and the second dielectric is one of AlON and Al 2 O 3. 5. The carbon nanotube transistor of claim 1 wherein at least one of the first dielectric and the second dielectric induces an electrostatic doping effect in the carbon nanotube. 6. The carbon nanotube transistor of claim 1, wherein the p-n junction is oriented along a longitudinal axis of the carbon nanotube. 7. The carbon nanotube transistor of claim 6, wherein the orientation of the p-n junction increases an ON/OFF ratio of a drain-source current of the transistor over an ON/OFF ratio of a transistor without the p-n junction. 8. (canceled) 9. (canceled) 10. (canceled) 11. (canceled) 12. (canceled) 13. (canceled) 14. (canceled) 15. A carbon nanotube transistor, comprising: a carbon nanotube configured to traverse a gate electrode of the transistor, at least one of a source electrode and a drain electrode of the transistor, and a space region of between the gate electrode and the at least one of the source electrode and the drain electrode, wherein the carbon nanotube is doped at the gate region and in the space region to form a p-n junction. 16. The carbon nanotube transistor of claim 15, further comprising a first dielectric configured to provide one of an n-type doping and a p-type doping to the carbon nanotube at the gate electrode and a second dielectric configured to provide the other of the n-type doping and the p-type doping to the carbon nanotube in the space region. 17. The carbon nanotube transistor of claim 16, wherein the first dielectric is one of AlON and HfO 2 and the second dielectric is one of AlON and Al 2 O 3. 18. The carbon nanotube transistor of claim 16, wherein at least one of the first dielectric and the second dielectric induces an electrostatic doping effect in the carbon nanotube. 19. The carbon nanotube transistor of claim 16, wherein the p-n junction is oriented along a longitudinal axis of the carbon nanotube. 20. The carbon nanotube transistor of claim 19, wherein the orientation of the p-n junction increases an ON/OFF ratio of a drain-source current of the transistor over an ON/OFF ratio of a transistor having an undoped carbon nanotube.

Description

The present disclosure claims priority from U.S. Provisional Application Ser. No. 61/976,188, titled “FORMING PN JUNCTION CONTACTS BY DIFFERENT DIELECTRICS,” filed on Apr. 7, 2014.

The present invention relates to carbon nanotube transistors and, in particular, to methods for reducing device OFF current and increasing the performance of carbon nanotube transistors.

Thin-film transistors are commonly used in display technologies, such as liquid crystal displays (LCD). Carbon nanotube thin-film transistors have the potential to replace standard thin-film transistors that are based on amorphous silicon or poly-silicon material. These transistors generally have higher mobility than Si-based thin-film transistors and can be fabricated with lower cost. The capability of depositing carbon nanotube thin film at room temperature allows the device fabrication on flexible substrates, enabling other new applications such as flexible electronics and displays. One important device performance parameter is the ratio between ON source-drain current (where both gate-source and drain-source biases are at full bias) and OFF source-drain current (where drain-source is at full bias and gate-source is at zero bias). Despite the abovementioned advantages of using carbon nanotube thin-film material, transistors with this material potentially suffer from larger OFF current due to Schottky barrier contacts. The ambipolar current from the thermionic emission over the Schottky barrier height greatly limits device ON/OFF ratio, in particular with a larger voltage applied between the source and the drain.

Record as JSON
{
  "publication_number": "US2015287942A1",
  "country": "US",
  "kind": "A1",
  "title": "Forming pn junction contacts by different dielectrics",
  "abstract": "A carbon nanotube transistor and method of manufacturing a carbon nanotube transistor is disclosed. The carbon nanotube transistor includes a carbon nanotube on a substrate, a gate electrode deposited on the carbon nanotube, and at least one of a source electrode and a drain electrode deposited on the carbon nanotube and separated from the gate electrode by a space region. The carbon nanotube is doped at the gate electrode an in the space region to form a p-n junction.",
  "claims": [
    "1. A carbon nanotube transistor, comprising: one or more carbon nanotubes on a substrate; a gate structure including a gate electrode deposited on the carbon nanotube; and at least one of a source electrode and a drain electrode deposited on the one or more carbon nanotube and separated from the gate electrode by a space region, wherein the carbon nanotube is doped at the gate electrode and in the space region to form a p-n junction. 2. The carbon nanotube transistor of claim 1 further comprising a first dielectric configured to provide a first doping to the carbon nanotube at the gate electrode and a second dielectric configured to provide a second doping to the carbon nanotube in the space region to form the p-n junction. 3. The carbon nanotube transistor of claim 2, wherein the first doping is one of an n-type doping and a p-type doping and the second doping is the other of the n-type doping and the p-type doping. 4. The carbon nanotube transistor of claim 3, wherein the first dielectric is one of AlON and HfO 2 and the second dielectric is one of AlON and Al 2 O 3. 5. The carbon nanotube transistor of claim 1 wherein at least one of the first dielectric and the second dielectric induces an electrostatic doping effect in the carbon nanotube. 6. The carbon nanotube transistor of claim 1, wherein the p-n junction is oriented along a longitudinal axis of the carbon nanotube. 7. The carbon nanotube transistor of claim 6, wherein the orientation of the p-n junction increases an ON/OFF ratio of a drain-source current of the transistor over an ON/OFF ratio of a transistor without the p-n junction. 8. (canceled) 9. (canceled) 10. (canceled) 11. (canceled) 12. (canceled) 13. (canceled) 14. (canceled) 15. A carbon nanotube transistor, comprising: a carbon nanotube configured to traverse a gate electrode of the transistor, at least one of a source electrode and a drain electrode of the transistor, and a space region of between the gate electrode and the at least one of the source electrode and the drain electrode, wherein the carbon nanotube is doped at the gate region and in the space region to form a p-n junction. 16. The carbon nanotube transistor of claim 15, further comprising a first dielectric configured to provide one of an n-type doping and a p-type doping to the carbon nanotube at the gate electrode and a second dielectric configured to provide the other of the n-type doping and the p-type doping to the carbon nanotube in the space region. 17. The carbon nanotube transistor of claim 16, wherein the first dielectric is one of AlON and HfO 2 and the second dielectric is one of AlON and Al 2 O 3. 18. The carbon nanotube transistor of claim 16, wherein at least one of the first dielectric and the second dielectric induces an electrostatic doping effect in the carbon nanotube. 19. The carbon nanotube transistor of claim 16, wherein the p-n junction is oriented along a longitudinal axis of the carbon nanotube. 20. The carbon nanotube transistor of claim 19, wherein the orientation of the p-n junction increases an ON/OFF ratio of a drain-source current of the transistor over an ON/OFF ratio of a transistor having an undoped carbon nanotube."
  ],
  "description_excerpt": "The present disclosure claims priority from U.S. Provisional Application Ser. No. 61/976,188, titled “FORMING PN JUNCTION CONTACTS BY DIFFERENT DIELECTRICS,” filed on Apr. 7, 2014.\n\nThe present invention relates to carbon nanotube transistors and, in particular, to methods for reducing device OFF current and increasing the performance of carbon nanotube transistors.\n\nThin-film transistors are commonly used in display technologies, such as liquid crystal displays (LCD). Carbon nanotube thin-film transistors have the potential to replace standard thin-film transistors that are based on amorphous silicon or poly-silicon material. These transistors generally have higher mobility than Si-based thin-film transistors and can be fabricated with lower cost. The capability of depositing carbon nanotube thin film at room temperature allows the device fabrication on flexible substrates, enabling other new applications such as flexible electronics and displays. One important device performance parameter is the ratio between ON source-drain current (where both gate-source and drain-source biases are at full bias) and OFF source-drain current (where drain-source is at full bias and gate-source is at zero bias). Despite the abovementioned advantages of using carbon nanotube thin-film material, transistors with this material potentially suffer from larger OFF current due to Schottky barrier contacts. The ambipolar current from the thermionic emission over the Schottky barrier height greatly limits device ON/OFF ratio, in particular with a larger voltage applied between the source and the drain.",
  "cpc": [
    "H01L 51/0541",
    "H01L 51/002",
    "H01L 51/0048",
    "H01L 51/0525",
    "H01L 51/0558",
    "H01L 51/105",
    "H10D 62/118",
    "H10D 62/119",
    "H10D 62/121",
    "H10K 10/46",
    "H10K 10/464",
    "H10K 10/468",
    "H10K 10/472",
    "H10K 10/484",
    "H10K 10/84",
    "H10K 2102/00",
    "H10K 71/30",
    "H10K 85/221",
    "H10P 14/3464",
    "H10W 20/0554"
  ],
  "ipc": [
    "H10D 62/10",
    "H10K 99/00",
    "H01L 21/02"
  ],
  "assignees": [
    "International Business Machines Corp"
  ],
  "inventors": [
    "Qing Cao",
    "Shu-Jen Han"
  ],
  "filing_date": "2015-02-10",
  "publication_date": "2015-10-08",
  "priority_date": "2014-04-07",
  "application_number": "US-201514618618-A",
  "family_id": "54210504",
  "cited_by_count": 22
}

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