3D stacked multilayer semiconductor memory using doped select transistor channel

{
  "publication_number": "US10090316B2",
  "country": "US",
  "kind": "B2",
  "title": "3D stacked multilayer semiconductor memory using doped select transistor channel",
  "abstract": "In 3D stacked multilayer semiconductor memories including NAND and NOR flash memories, a lightly boron-doped layer is formed on top of a heavily boron-doped layer to form a select transistor, wherein the former serves as a channel of the select transistor and the latter serves as an isolation region which isolates the select transistor from a memory transistor.",
  "claims": [
    "1. 3D stacked multilayer semiconductor memory comprising: memory transistors constituted by heavily doped N-type semiconductor layers and lightly doped or undoped P-type semiconductor layers alternately layered with one another in a stacking direction, each layer extending in a longitudinal direction perpendicular to the stacking direction; and select transistors constituted by lightly doped P-type semiconductor layers and heavily doped P-type semiconductor layers alternately layered with one another, said select transistors being provided with gate electrodes, wherein the lightly doped P-type semiconductor layers of the select transistors are connected, continuously in the longitudinal direction, to one ends of the heavily doped N-type semiconductor layers of the memory transistors, respectively, and the heavily doped P-type semiconductor layers of the select transistors are connected, continuously in the longitudinal direction, to one ends of the lightly doped or undoped P-type semiconductor layers of the memory transistors, respectively, and wherein the lightly doped P-type semiconductor layers of the select transistor function as channels to select one of the heavily doped N-type semiconductor layers when applying voltage to the gate electrodes, and the heavily doped P-type semiconductor layers of the select transistors function as isolators to isolate the heavily doped P-type semiconductor layers from the lightly doped or undoped P-type semiconductor layers of the memory transistors.",
    "2. The 3D stacked multilayer semiconductor memory according to claim 1, wherein the lightly doped P-type semiconductor layers of the select transistors are lightly boron-doped layers formed by doping boron to layers identical to the heavily doped N-type semiconductor layers of the memory transistors, and the heavily doped P-type semiconductor layers of the select transistors are heavily boron-doped layers formed by doping boron to layers identical to the lightly doped or undoped P-type semiconductor layers of the memory transistors.",
    "3. The 3D stacked multilayer semiconductor memory according to claim 1, wherein the heavily doped N-type semiconductor layers of the memory transistors are heavily phosphorous-doped silicon layers, and the lightly doped or undoped P-type semiconductor layers of the memory transistors are undoped SiGe layers.",
    "4. The 3D stacked multilayer semiconductor memory according to claim 1, wherein a side of each select transistor opposite to a side connected to the corresponding memory transistor is connected to a bit line or source line, wherein only one select transistor is provided between the bit line or source line and each memory transistor.",
    "5. The 3D stacked multilayer semiconductor memory according to claim 1, wherein the select transistors, each constituted by the lightly doped P-type semiconductor layer, and the underlying heavily doped P-type semiconductor layer, are arranged so as to be aligned in the stacking direction.",
    "6. The 3D stacked multilayer semiconductor memory according to claim 1, wherein the select transistors, each constituted by the lightly doped P-type semiconductor layer and the underlying heavily doped P-type semiconductor layer, are arranged so as to form a staircase in the longitudinal direction.",
    "7. The 3D stacked multilayer semiconductor memory according to claim 6, wherein a space above the staircase is filled with a heavily doped N-type semiconductor in contact with the staircase.",
    "8. The 3D stacked multilayer semiconductor memory according to claim 7, wherein the heavily doped N-type semiconductor is phosphorous-doped poly-Si.",
    "9. A method of fabricating the 3D stacked multilayer semiconductor memory of claim 5, comprising: stacking lightly doped or undoped P-type semiconductor layers and heavily doped N-type semiconductor layers alternately with one another in the stacking direction for memory transistors; forming a column using the stacked layers so as to form a stacked layer structure having a column shape; forming a boron-doped film on the stacked layer structure having the column shape only in an area where select transistors are to be formed in the stacking direction, by lithograph and etching; and annealing the stacked layer structure having the boron-doped film to thermally remove the boron-doped film while doping boron to a portion of each lightly doped or undoped P-type semiconductor layer and a portion of each heavily doped N-type semiconductor layer where the select transistors are to be formed, whereby the portion of each lightly doped or undoped P-type semiconductor layer and the portion of each heavily doped N-type semiconductor layer are converted to a heavily doped P-type semiconductor layer and a lightly doped P-type semiconductor layer of the select transistors, respectively.",
    "10. The method according to claim 9, wherein the boron-doped film is constituted by heavily doped boron silicon glass.",
    "11. The method according to claim 10, wherein the lightly doped or undoped Ptype semiconductor layers are constituted by undoped SiGe, and the heavily doped N-type semiconductor layers are constituted by heavily phosphorous-doped silicon.",
    "12. A method of fabricating the 3D stacked multilayer semiconductor memory of claim 7, comprising: stacking lightly doped or undoped P-type semiconductor layers and heavily doped N-type semiconductor layers alternately with one another in a stacking direction for memory transistors; forming a staircase in the stacked layer structure in a longitudinal direction by removing a portion of the stacked layer structure by lithography and etching; doping boron to a portion of the staircase by ion implantation where select transistors are to be formed, whereby a portion of each lightly doped or undoped Ptype semiconductor layer and a portion of each heavily doped N-type semiconductor layer constituting the staircase are converted to a heavily doped P-type semiconductor layer and a lightly doped P-type semiconductor layer of the select transistors, respectively; and filling a space formed by removing the portion above the staircase with a heavily doped N-type semiconductor.",
    "13. The method according to claim 12, wherein the lightly doped or undoped Ptype semiconductor layers are constituted by undoped SiGe, and the heavily doped N-type semiconductor layers are constituted by heavily phosphorous-doped silicon."
  ],
  "description_excerpt": "The present invention generally relates to 3D stacked multilayer semiconductor memories such as NAND and NOR memories.\n\nAs 3D stacked multilayer semiconductor memories, several candidates have been pursued, including NAND and NOR memories. One approach is to utilize different types of semiconductors as stacking films. This method is beneficial in that a channel can be formed with a crystal semiconductor that enables much faster operation than a poly-Si channel that is constructed by stacking a poly-Si layer and a SiO layer. One example using such a crystal semiconductor is described in IEDM 2009, p 637-640, by A. Hubert et al. wherein a Si - SiGe stacked structure is utilized. Another example is described in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 4, APRIL 2011, p 1006-1014, by Jan-Gn Yun et al. These two examples focus on NAND flash memories. Other applications including logic circuits are described in U.S. Pat. No. 8,581,349 B1. In stacking of multiple semiconductors such as those in the above examples, one issue to be worked on when using a select transistor is how to perform doping in a channel region of a select transistor because a doping concentration of the select transistor channel has to be different from that of a channel of a memory transistor. Another issue to be worked on when using a select transistor is how to establish isolation of the select transistor from the memory transistor. In conventional NAND and NOR memories, isolation is not needed because every memory transistor is aligned serial to each other, but a select transistor requires isolation from a memory transistor.",
  "cpc": [
    "H01L 27/11578",
    "H01L 27/1157",
    "H01L 27/11582",
    "H10B 43/20",
    "H10B 43/27",
    "H10B 43/35",
    "H10B 43/50"
  ],
  "ipc": [
    "H10B 43/20",
    "H10B 43/27",
    "H10B 43/35",
    "H10B 69/00"
  ],
  "assignees": [
    "ASM IP Holding BV"
  ],
  "inventors": [
    "Fumio Ootsuka"
  ],
  "filing_date": "2016-09-01",
  "publication_date": "2018-10-02",
  "grant_date": "2018-10-02",
  "priority_date": "2016-09-01",
  "application_number": "US-201615254605-A",
  "family_id": "61243492",
  "cited_by_count": 471,
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