Semiconductor device having damascene interconnection structure that prevents void formation between interconnections having transparent dielectric substrate

{
  "publication_number": "US2010270675A1",
  "country": "US",
  "kind": "A1",
  "title": "Semiconductor device having damascene interconnection structure that prevents void formation between interconnections having transparent dielectric substrate",
  "abstract": "A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which includes a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the first conductive layer and the first barrier layer. Accordingly, the semiconductor device can avoid a problem where the material of the first main interconnection transfers from a portion connected to the second interconnection due to electromigration to form a void, with the result that the first interconnection is disconnected from the second interconnection.",
  "claims": [
    "1. A semiconductor device comprising: a first insulating layer having a through hole; a first interconnection comprised a first conductive layer, a first barrier layer, and a first main interconnection, the first conductive layer formed on the first insulating layer in the first through hole, the first barrier layer formed on the first conductive layer, and the first main interconnection formed on the first barrier layer so as to bury the through hole; and a second interconnection connected to one of the first conductive layer and the first barrier layer. 2. A method of forming a semiconductor device comprising: forming a first insulating layer having a through hole; forming a first interconnection comprised a first conductive layer, a first barrier layer, and a first main interconnection, the first conductive layer formed on the first insulating layer in the first through hole, the first barrier layer formed on the first conductive layer, and the first main interconnection formed on the first barrier layer so as to bury the through hole; and forming a second interconnection connected to one of the first conductive layer and the first barrier layer."
  ],
  "description_excerpt": "1. Field of the Invention\n\nThe present invention generally relates to a semiconductor substrate, and more particularly, the present invention relates to a damascene interconnection structure.\n\nThis application is a counterpart of Japanese application Serial Number 163304/1998, filed Jun. 11, 1998, the subject matter of which is incorporated herein by reference.\n\n2. Description of the Related Art\n\nIn general, it is difficult to form a pattern by etching a Copper (Cu) interconnection. In a formation of the Cu interconnection, an insulating layer such as a SiO 2 or BPSG is formed on a semiconductor substrate. Then, a recess is formed in the insulating layer so as to shape the Cu interconnection. Then, Cu is buried in the recess. As a result, the Cu interconnection buried in the recess is a so-called damascene interconnection, which is formed on the semiconductor substrate.\n\nSuch a damascene interconnection is formed as shown in FIG. 1A-FIG. 1 D. FIG. 1A-FIG. 1 D are cross sectional views showing a damascene interconnection structure of a conventional art.\n\nA first interconnection pattern recess is formed using photolithography techniques and etching techniques in a first SiO 2 film 12 having a thickness of 1 μm on the semiconductor substrate 10. Then, a barrier layer 16 such as a TiN is formed on the first SiO 2 film 12 in the first interconnection pattern recess. Then, Cu is formed on the entire surface and the Cu is polished with alkaline solution having a colloidal-silica, so-called CMP (chemical mechanical polishing) method.",
  "cpc": [
    "H10W 20/084",
    "H10W 20/033",
    "H10W 20/036",
    "H10W 20/039",
    "H10W 20/083",
    "H10W 20/425",
    "H10W 20/435"
  ],
  "ipc": [
    "H01L 21/3205",
    "H01L 21/768",
    "H10W 20/43"
  ],
  "assignees": [
    "Oki Semiconductor Co Ltd"
  ],
  "inventors": [
    "Yusuke Harada"
  ],
  "filing_date": "2010-07-02",
  "publication_date": "2010-10-28",
  "priority_date": "1998-06-11",
  "application_number": "US-82963310-A",
  "family_id": "15771292",
  "cited_by_count": 522,
  "citations": [
    "US4916521A",
    "US5889328A",
    "US5510651A",
    "US5561327A",
    "US5391517A",
    "US5444022A",
    "US5691572A",
    "US5666007A",
    "US5798299A",
    "US5571751A",
    "US5614764A",
    "US5864179A",
    "US6087250A",
    "US5674787A",
    "US5883434A",
    "US5840624A",
    "US6077774A",
    "US6008117A",
    "US5792705A",
    "US6037278A",
    "US5863835A",
    "US5981377A",
    "US6040627A",
    "US6028362A",
    "US5969422A",
    "US6133139A",
    "US6093635A",
    "US6008118A",
    "US5939788A",
    "US6037250A",
    "US6759747B2",
    "US6030896A"
  ]
}