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Patent · US9305836B1 · B1 · US

Air gap semiconductor structure with selective cap bilayer

(11) Publication number
US9305836B1
(21) Application number
14/536,751
(22) Filing date
2014-11-10
(30) Priority date
2014-11-10
(43) Publication date
2016-04-05
(45) Date of grant
2016-04-05
(51) IPC
H01L 21/311; H01L 21/768; H10W 20/43
(52) CPC
  • H10W Generic packages, interconnections, connectors or other constructional details of devices covered by class H10: 20/425, 20/037, 20/048, 20/0523, 20/0526, 20/072, 20/077, 20/46, 20/47, 20/495
  • H01L Semiconductor devices; electric solid state devices not otherwise provided for: 21/31111, 21/76802, 21/7682, 21/76834, 21/7685, 23/528, 23/53209, 23/53223, 23/53238, 23/53252, 23/53266, 23/5329
  • H10P Generic processes or apparatus for the manufacture or treatment of devices covered by class H10: 14/43, 14/46, 50/283
(73) Assignee
International Business Machines Corp
(72) Inventors
Stephen M. Gates; Elbert E. Huang; Dimitri R. Kioussis; Christopher J. Penny; Deepika Priyadarshini
(54) Title
Air gap semiconductor structure with selective cap bilayer
(57) Abstract

A semiconductor substrate including one or more conductors is provided. A first layer and a second layer are deposited on the top surface of the conductors. A dielectric cap layer is formed over the semiconductor substrate and air gaps are etched into the dielectric layer. The result is a bilayer cap air gap structure with effective electrical performance.

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Claims (10)

  1. A semiconductor structure comprising: a dielectric layer present on a semiconductor substrate; one or more conductors within the dielectric layer, wherein the one or more conductors have a top surface; a bilayer cap present on the one or more conductors, wherein the bilayer cap comprises a first layer and a second layer, and wherein the second layer comprises one or more of: CoCH, CoSiNCH, CoSi x, and a capping material including SiCH, SiCNH, amorphous C, and amorphous CH; and a plurality of air gaps, wherein the air gaps are etched into the dielectric layer.
  2. The semiconductor structure of claim 1, wherein the first layer comprises an adhesive layer, and is configured to be in adhesive contact with the one or more conductors.
  3. The semiconductor structure of claim 1, wherein the second layer comprises a protective layer, and is configured to be in adhesive contact with the first layer.
  4. The semiconductor structure of claim 1, wherein the bilayer cap is a self-aligned bilayer cap.
  5. The semiconductor structure of claim 1, wherein the first layer comprises one or more metals including: cobalt, manganese, tantalum, ruthenium, aluminum, nickel, tungsten, platinum, palladium, and rhenium.
  6. The semiconductor structure of claim 1, wherein the first layer comprises an electroless metal capping layer, wherein the electroless metal capping layer comprises one or more of: CoWP, CoWB, NiWP, and a selective CVD Ru cap.
  7. The semiconductor structure of claim 1, wherein the second layer comprises a metal compound, wherein the metal compound includes: C, Si, N, and H.
  8. A semiconductor structure comprising: a dielectric layer present on a semiconductor substrate; one or more Cu conductors within the dielectric layer, wherein the one or more Cu conductors have a top surface; a bilayer cap present on the one or more Cu conductors, wherein the bilayer cap comprises a first layer deposited on the top surface of the Cu conductors and a second layer deposited on the first layer, wherein the second layer comprises one or more of: a metal containing alloy including MC x, MN y, MC x N y, MSi x C y, MSi x N y, and MSi x N y C z, wherein M is selected from Co, Mn, Ta, Re, Al, Ni, W, Pt, Pd, Re; a plurality of air gaps, wherein the air gaps are etched to a selected depth within the dielectric layer; and a conformal cap layer deposited on, at least, the top surface of the dielectric layer, and a non-conformal cap layer deposited on, at least, the top surface of the deposited conformal cap layer.
  9. The semiconductor structure of claim 8, wherein the bilayer cap comprises a repeated plurality of first layers and second layers to form a multiple layer cap.
  10. The semiconductor structure of claim 8, wherein the plurality of air gaps are etched to a selected depth range from 2 nm to 50 nm below the top surface of the one or more conductors.

Description

The present invention relates generally to semiconductor devices, and more particularly to the formation of air gap structures in a semiconductor device with a bilayer selective cap.

Semiconductor devices generally include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. To improve the performance of the circuits, low k dielectric materials, having a dielectric constant of less than silicon dioxide, are used between circuits as inter-layer dielectric (ILD) to reduce capacitance. Interconnect structures made of metal lines are usually formed in and around the ILD material to connect elements of the circuits. Within a typical interconnect structure, metal lines run parallel to the semiconductor substrate. An interconnect structure may consist of multilevel or multilayered schemes, such as, single or dual damascene wiring structures.

Manufacture of a semiconductor device, also called an electronic device or integrated circuit, is normally divided into two major phases. The “front end of the line” (FEOL) is dedicated to the creation of all transistors in the body of the semiconductor devices, and the “back end of the line” (BEOL) creates the metal interconnect structures which connect the transistors to each other, as well as provide power to the devices. Once all active components are created, the BEOL manufacturing begins.

Air gap structures, which may be used in flash memory chips, are known to reduce capacitance in the interconnect back end of the line (BEOL) structures of high performance integrated circuits.

Citations (15)

  • US20080026541A1
  • US7666753B2
  • US7741228B2
  • US7635646B2
  • US7514361B2
  • US20090075470A1
  • US20090200636A1
  • US7842600B2
  • US8274155B2
  • US8399350B2
  • US20110221062A1
  • US8304906B2
  • US8779590B2
  • US8716127B2
  • US20130292835A1
Record as JSON
{
  "publication_number": "US9305836B1",
  "country": "US",
  "kind": "B1",
  "title": "Air gap semiconductor structure with selective cap bilayer",
  "abstract": "A semiconductor substrate including one or more conductors is provided. A first layer and a second layer are deposited on the top surface of the conductors. A dielectric cap layer is formed over the semiconductor substrate and air gaps are etched into the dielectric layer. The result is a bilayer cap air gap structure with effective electrical performance.",
  "claims": [
    "1. A semiconductor structure comprising: a dielectric layer present on a semiconductor substrate; one or more conductors within the dielectric layer, wherein the one or more conductors have a top surface; a bilayer cap present on the one or more conductors, wherein the bilayer cap comprises a first layer and a second layer, and wherein the second layer comprises one or more of: CoCH, CoSiNCH, CoSi x, and a capping material including SiCH, SiCNH, amorphous C, and amorphous CH; and a plurality of air gaps, wherein the air gaps are etched into the dielectric layer.",
    "2. The semiconductor structure of claim 1, wherein the first layer comprises an adhesive layer, and is configured to be in adhesive contact with the one or more conductors.",
    "3. The semiconductor structure of claim 1, wherein the second layer comprises a protective layer, and is configured to be in adhesive contact with the first layer.",
    "4. The semiconductor structure of claim 1, wherein the bilayer cap is a self-aligned bilayer cap.",
    "5. The semiconductor structure of claim 1, wherein the first layer comprises one or more metals including: cobalt, manganese, tantalum, ruthenium, aluminum, nickel, tungsten, platinum, palladium, and rhenium.",
    "6. The semiconductor structure of claim 1, wherein the first layer comprises an electroless metal capping layer, wherein the electroless metal capping layer comprises one or more of: CoWP, CoWB, NiWP, and a selective CVD Ru cap.",
    "7. The semiconductor structure of claim 1, wherein the second layer comprises a metal compound, wherein the metal compound includes: C, Si, N, and H.",
    "8. A semiconductor structure comprising: a dielectric layer present on a semiconductor substrate; one or more Cu conductors within the dielectric layer, wherein the one or more Cu conductors have a top surface; a bilayer cap present on the one or more Cu conductors, wherein the bilayer cap comprises a first layer deposited on the top surface of the Cu conductors and a second layer deposited on the first layer, wherein the second layer comprises one or more of: a metal containing alloy including MC x, MN y, MC x N y, MSi x C y, MSi x N y, and MSi x N y C z, wherein M is selected from Co, Mn, Ta, Re, Al, Ni, W, Pt, Pd, Re; a plurality of air gaps, wherein the air gaps are etched to a selected depth within the dielectric layer; and a conformal cap layer deposited on, at least, the top surface of the dielectric layer, and a non-conformal cap layer deposited on, at least, the top surface of the deposited conformal cap layer.",
    "9. The semiconductor structure of claim 8, wherein the bilayer cap comprises a repeated plurality of first layers and second layers to form a multiple layer cap.",
    "10. The semiconductor structure of claim 8, wherein the plurality of air gaps are etched to a selected depth range from 2 nm to 50 nm below the top surface of the one or more conductors."
  ],
  "description_excerpt": "The present invention relates generally to semiconductor devices, and more particularly to the formation of air gap structures in a semiconductor device with a bilayer selective cap.\n\nSemiconductor devices generally include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. To improve the performance of the circuits, low k dielectric materials, having a dielectric constant of less than silicon dioxide, are used between circuits as inter-layer dielectric (ILD) to reduce capacitance. Interconnect structures made of metal lines are usually formed in and around the ILD material to connect elements of the circuits. Within a typical interconnect structure, metal lines run parallel to the semiconductor substrate. An interconnect structure may consist of multilevel or multilayered schemes, such as, single or dual damascene wiring structures.\n\nManufacture of a semiconductor device, also called an electronic device or integrated circuit, is normally divided into two major phases. The “front end of the line” (FEOL) is dedicated to the creation of all transistors in the body of the semiconductor devices, and the “back end of the line” (BEOL) creates the metal interconnect structures which connect the transistors to each other, as well as provide power to the devices. Once all active components are created, the BEOL manufacturing begins.\n\nAir gap structures, which may be used in flash memory chips, are known to reduce capacitance in the interconnect back end of the line (BEOL) structures of high performance integrated circuits.",
  "cpc": [
    "H10W 20/425",
    "H01L 21/31111",
    "H01L 21/76802",
    "H01L 21/7682",
    "H01L 21/76834",
    "H01L 21/7685",
    "H01L 23/528",
    "H01L 23/53209",
    "H01L 23/53223",
    "H01L 23/53238",
    "H01L 23/53252",
    "H01L 23/53266",
    "H01L 23/5329",
    "H10P 14/43",
    "H10P 14/46",
    "H10P 50/283",
    "H10W 20/037",
    "H10W 20/048",
    "H10W 20/0523",
    "H10W 20/0526",
    "H10W 20/072",
    "H10W 20/077",
    "H10W 20/46",
    "H10W 20/47",
    "H10W 20/495"
  ],
  "ipc": [
    "H01L 21/311",
    "H01L 21/768",
    "H10W 20/43"
  ],
  "assignees": [
    "International Business Machines Corp"
  ],
  "inventors": [
    "Stephen M. Gates",
    "Elbert E. Huang",
    "Dimitri R. Kioussis",
    "Christopher J. Penny",
    "Deepika Priyadarshini"
  ],
  "filing_date": "2014-11-10",
  "publication_date": "2016-04-05",
  "grant_date": "2016-04-05",
  "priority_date": "2014-11-10",
  "application_number": "US-201414536751-A",
  "family_id": "55589078",
  "cited_by_count": 491,
  "citations": [
    "US20080026541A1",
    "US7666753B2",
    "US7741228B2",
    "US7635646B2",
    "US7514361B2",
    "US20090075470A1",
    "US20090200636A1",
    "US7842600B2",
    "US8274155B2",
    "US8399350B2",
    "US20110221062A1",
    "US8304906B2",
    "US8779590B2",
    "US8716127B2",
    "US20130292835A1"
  ]
}

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