Patent · US11171098B2 · B2 · US

Package and manufacturing method thereof

(11) Publication number

US11171098B2

(21) Application number

16/548,826

(22) Filing date

2019-08-22

(30) Priority date

2018-09-27

(43) Publication date

2021-11-09

(45) Date of grant

2021-11-09

(51) IPC

H01L 23/00; H01L 23/31; H10W 74/01

(52) CPC

H10W Generic packages, interconnections, connectors or other constructional details of devices covered by class H10: 72/90, 70/09, 70/099, 70/60, 70/65, 70/655, 72/019, 72/073, 72/29, 72/874, 74/00, 74/014, 74/016, 74/111, 74/117, 90/00, 90/754
H01L Semiconductor devices; electric solid state devices not otherwise provided for: 21/565, 2224/02331, 2224/02333, 2224/02372, 2224/02379, 2224/0401, 23/3107, 24/03, 24/06, 24/09
H10P Generic processes or apparatus for the manufacture or treatment of devices covered by class H10: 72/74, 72/7424

(73) Assignee

Taiwan Semiconductor Manufacturing Co TSMC Ltd

(72) Inventors

Tian Hu; Hung-Jui Kuo; Yu-Hsiang Hu

(54) Title

Package and manufacturing method thereof

(57) Abstract

A package includes a first redistribution structure, a die, a plurality of conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure includes a composite dielectric layer, a plurality of under bump metallization patterns, a dielectric layer, and a plurality of conductive patterns. The composite dielectric layer includes a first sub-layer and a second sub-layer stacked on the first sub-layer. The under bump metallization patterns are over the first sub-layer and penetrate through the composite dielectric layer. The dielectric layer is disposed on the second sub-layer of the composite dielectric layer. The conductive patterns are embedded in the dielectric layer. The die and the conductive structures are on the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is over the conductive structures, the encapsulant, and the die.

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Claims (20)

A package, comprising: a first redistribution structure, comprising: a composite dielectric layer comprising a first sub-layer and a second sub-layer stacked on the first sub-layer; a plurality of under bump metallization patterns over the first sub-layer and penetrating through the composite dielectric layer; a dielectric layer disposed on the second sub-layer of the composite dielectric layer, wherein a surface of the dielectric layer has a roughness larger than 0 μm and less than or equal to 0.1 μm; and a plurality of conductive patterns embedded in the dielectric layer, wherein a surface of each of the plurality of conductive patterns has a roughness larger than 0 μm and less than or equal to 0.5 μm; a die and a plurality of conductive structures on the first redistribution structure; an encapsulant encapsulating the die and the plurality of conductive structures; and a second redistribution structure over the plurality of conductive structures, the encapsulant, and the die.
The package according to claim 1, wherein a thickness of the composite dielectric layer ranges between 2 μm and 60 μm.
The package according to claim 1, wherein a ratio of a thickness of each of the plurality of conductive patterns to a thickness of the composite dielectric layer ranges between 1:30 and 10:1.
The package according to claim 1, wherein a ratio of a thickness of the dielectric layer to a thickness of the composite dielectric layer ranges between 1:12 and 25:1.
The package according to claim 1, wherein a density of the first sub-layer and a density of the second sub-layer are the same.
The package according to claim 1, further comprising a plurality of conductive terminals disposed on the plurality of under bump metallization patterns.
The package according to claim 1, wherein the first sub-layer comprises fillers and the second sub-layer is free of filler.
The package according to claim 1, wherein the composite dielectric layer further comprises a third sub-layer sandwiched between the first sub-layer and the second sub-layer, and the third sub-layer comprises dye.
The package according to claim 1, wherein a thickness of the first sub-layer is different from a thickness of the second sub-layer.
A method of manufacturing a package, comprising: providing a carrier having a de-bonding layer formed thereon; forming a first redistribution structure on the de-bonding layer, comprising: forming a composite dielectric layer on the de-bonding layer, comprising: spin coating a first sub-layer on the de-bonding layer; curing the first sub-layer; spin coating a second sub-layer on the first sub-layer; and curing the second sub-layer; forming a plurality of conductive patterns on the composite dielectric layer; and forming a dielectric layer on the composite dielectric layer to cover the plurality of conductive patterns; forming a plurality of conductive structures over the first redistribution structure; placing a die over the first redistribution structure; encapsulating the plurality of conductive structures and the die by an encapsulant; and forming a second redistribution structure over the plurality of conductive structures, the encapsulant, and the die.
The method according to claim 10, wherein a rotational speed for spin coating the first sub-layer is larger than a rotational speed for spin coating the second sub-layer.
The method according to claim 10, wherein the first sub-layer is spin coated with a rotational speed of 350 rpm to 3500 rpm, and the second sub-layer is spin coated with a rotational speed of 300 rpm to 3000 rpm.
The method according to claim 10, further comprising: removing the de-bonding layer and the carrier from the first redistribution structure; forming a plurality of openings in the composite dielectric layer, wherein the plurality of openings penetrate through the first sub-layer and the second sub-layer to expose at least a portion of the plurality of conductive patterns; forming a plurality of under bump metallization patterns in the plurality of openings; and disposing a plurality of conductive terminals over the plurality of under bump metallization patterns.
The method according to claim 10, wherein the step of forming the composite dielectric layer further comprises: forming a third sub-layer between the first sub-layer and the second sub-layer, wherein the third sub-layer comprises dye.
The method according to claim 10, wherein a thickness of the composite dielectric layer ranges between 2 μm and 60 μm.
A method of manufacturing a package, comprising: providing a carrier having a de-bonding layer formed thereon; forming a first redistribution structure on the de-bonding layer, comprising: spin coating a buffer layer on the de-bonding layer; spin coating an auxiliary buffer layer on the buffer layer, wherein a material of the buffer layer is the same as a material of the auxiliary buffer layer, and a rotational speed for spin coating the buffer layer is larger than a rotational speed for spin coating the auxiliary buffer layer; forming a plurality of conductive patterns on the auxiliary buffer layer; and forming a dielectric layer on the auxiliary buffer layer to cover the plurality of conductive patterns; forming a plurality of conductive structures over the first redistribution structure; placing a die over the first redistribution structure; encapsulating the plurality of conductive structures and the die by an encapsulant; and forming a second redistribution structure over the plurality of conductive structures, the encapsulant, and the die.
The method according to claim 16, wherein the step of forming the first redistribution structure further comprises: curing the buffer layer before spin coating the auxiliary buffer layer; and curing the auxiliary buffer layer before forming the plurality of conductive patterns.
The method according to claim 16, wherein the buffer layer is spin coated with the rotational speed of 350 rpm to 3500 rpm, and the auxiliary buffer layer is spin coated with the rotational speed of 300 rpm to 3000 rpm.
The method according to claim 16, further comprising: removing the de-bonding layer and the carrier from the first redistribution structure; forming a plurality of openings in the buffer layer and the auxiliary buffer layer, wherein the plurality of openings penetrate through the buffer layer and the auxiliary buffer layer to expose at least a portion of the plurality of conductive patterns; forming a plurality of under bump metallization patterns in the plurality of openings; and disposing a plurality of conductive terminals over the plurality of under bump metallization patterns.
The method according to claim 16, wherein the step of forming the first redistribution structure further comprises: forming a colored layer between the buffer layer and the auxiliary buffer layer, wherein the colored layer comprises dye.

Description

The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more of the smaller components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than previous packages. Currently, integrated fan-out packages are becoming increasingly popular for their compactness. How to ensure the reliability of the integrated fan-out packages has become a challenge in the field.

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1A to FIG. 1O are schematic cross-sectional views illustrating a manufacturing process of a package in accordance with some embodiments of the disclosure.

FIG. 2 is a schematic cross-sectional view illustrating a package-on-package structure in accordance with some embodiments of the disclosure.

FIG. 3 is a schematic cross-sectional view illustrating a package in accordance with some alternative embodiments of the disclosure.

Citations (17)

US8350381B2
US9048233B2
US9064879B2
US9372206B2
US20130105991A1
US9000584B2
US9111949B2
US9263511B2
US9048222B2
US9368460B2
US9281254B2
US20150287700A1
US20160013144A1
US9496189B2
US20160071820A1
US20160126220A1
US20160379965A1

Record as JSON

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  "publication_number": "US11171098B2",
  "country": "US",
  "kind": "B2",
  "title": "Package and manufacturing method thereof",
  "abstract": "A package includes a first redistribution structure, a die, a plurality of conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure includes a composite dielectric layer, a plurality of under bump metallization patterns, a dielectric layer, and a plurality of conductive patterns. The composite dielectric layer includes a first sub-layer and a second sub-layer stacked on the first sub-layer. The under bump metallization patterns are over the first sub-layer and penetrate through the composite dielectric layer. The dielectric layer is disposed on the second sub-layer of the composite dielectric layer. The conductive patterns are embedded in the dielectric layer. The die and the conductive structures are on the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is over the conductive structures, the encapsulant, and the die.",
  "claims": [
    "1. A package, comprising: a first redistribution structure, comprising: a composite dielectric layer comprising a first sub-layer and a second sub-layer stacked on the first sub-layer; a plurality of under bump metallization patterns over the first sub-layer and penetrating through the composite dielectric layer; a dielectric layer disposed on the second sub-layer of the composite dielectric layer, wherein a surface of the dielectric layer has a roughness larger than 0 μm and less than or equal to 0.1 μm; and a plurality of conductive patterns embedded in the dielectric layer, wherein a surface of each of the plurality of conductive patterns has a roughness larger than 0 μm and less than or equal to 0.5 μm; a die and a plurality of conductive structures on the first redistribution structure; an encapsulant encapsulating the die and the plurality of conductive structures; and a second redistribution structure over the plurality of conductive structures, the encapsulant, and the die.",
    "2. The package according to claim 1, wherein a thickness of the composite dielectric layer ranges between 2 μm and 60 μm.",
    "3. The package according to claim 1, wherein a ratio of a thickness of each of the plurality of conductive patterns to a thickness of the composite dielectric layer ranges between 1:30 and 10:1.",
    "4. The package according to claim 1, wherein a ratio of a thickness of the dielectric layer to a thickness of the composite dielectric layer ranges between 1:12 and 25:1.",
    "5. The package according to claim 1, wherein a density of the first sub-layer and a density of the second sub-layer are the same.",
    "6. The package according to claim 1, further comprising a plurality of conductive terminals disposed on the plurality of under bump metallization patterns.",
    "7. The package according to claim 1, wherein the first sub-layer comprises fillers and the second sub-layer is free of filler.",
    "8. The package according to claim 1, wherein the composite dielectric layer further comprises a third sub-layer sandwiched between the first sub-layer and the second sub-layer, and the third sub-layer comprises dye.",
    "9. The package according to claim 1, wherein a thickness of the first sub-layer is different from a thickness of the second sub-layer.",
    "10. A method of manufacturing a package, comprising: providing a carrier having a de-bonding layer formed thereon; forming a first redistribution structure on the de-bonding layer, comprising: forming a composite dielectric layer on the de-bonding layer, comprising: spin coating a first sub-layer on the de-bonding layer; curing the first sub-layer; spin coating a second sub-layer on the first sub-layer; and curing the second sub-layer; forming a plurality of conductive patterns on the composite dielectric layer; and forming a dielectric layer on the composite dielectric layer to cover the plurality of conductive patterns; forming a plurality of conductive structures over the first redistribution structure; placing a die over the first redistribution structure; encapsulating the plurality of conductive structures and the die by an encapsulant; and forming a second redistribution structure over the plurality of conductive structures, the encapsulant, and the die.",
    "11. The method according to claim 10, wherein a rotational speed for spin coating the first sub-layer is larger than a rotational speed for spin coating the second sub-layer.",
    "12. The method according to claim 10, wherein the first sub-layer is spin coated with a rotational speed of 350 rpm to 3500 rpm, and the second sub-layer is spin coated with a rotational speed of 300 rpm to 3000 rpm.",
    "13. The method according to claim 10, further comprising: removing the de-bonding layer and the carrier from the first redistribution structure; forming a plurality of openings in the composite dielectric layer, wherein the plurality of openings penetrate through the first sub-layer and the second sub-layer to expose at least a portion of the plurality of conductive patterns; forming a plurality of under bump metallization patterns in the plurality of openings; and disposing a plurality of conductive terminals over the plurality of under bump metallization patterns.",
    "14. The method according to claim 10, wherein the step of forming the composite dielectric layer further comprises: forming a third sub-layer between the first sub-layer and the second sub-layer, wherein the third sub-layer comprises dye.",
    "15. The method according to claim 10, wherein a thickness of the composite dielectric layer ranges between 2 μm and 60 μm.",
    "16. A method of manufacturing a package, comprising: providing a carrier having a de-bonding layer formed thereon; forming a first redistribution structure on the de-bonding layer, comprising: spin coating a buffer layer on the de-bonding layer; spin coating an auxiliary buffer layer on the buffer layer, wherein a material of the buffer layer is the same as a material of the auxiliary buffer layer, and a rotational speed for spin coating the buffer layer is larger than a rotational speed for spin coating the auxiliary buffer layer; forming a plurality of conductive patterns on the auxiliary buffer layer; and forming a dielectric layer on the auxiliary buffer layer to cover the plurality of conductive patterns; forming a plurality of conductive structures over the first redistribution structure; placing a die over the first redistribution structure; encapsulating the plurality of conductive structures and the die by an encapsulant; and forming a second redistribution structure over the plurality of conductive structures, the encapsulant, and the die.",
    "17. The method according to claim 16, wherein the step of forming the first redistribution structure further comprises: curing the buffer layer before spin coating the auxiliary buffer layer; and curing the auxiliary buffer layer before forming the plurality of conductive patterns.",
    "18. The method according to claim 16, wherein the buffer layer is spin coated with the rotational speed of 350 rpm to 3500 rpm, and the auxiliary buffer layer is spin coated with the rotational speed of 300 rpm to 3000 rpm.",
    "19. The method according to claim 16, further comprising: removing the de-bonding layer and the carrier from the first redistribution structure; forming a plurality of openings in the buffer layer and the auxiliary buffer layer, wherein the plurality of openings penetrate through the buffer layer and the auxiliary buffer layer to expose at least a portion of the plurality of conductive patterns; forming a plurality of under bump metallization patterns in the plurality of openings; and disposing a plurality of conductive terminals over the plurality of under bump metallization patterns.",
    "20. The method according to claim 16, wherein the step of forming the first redistribution structure further comprises: forming a colored layer between the buffer layer and the auxiliary buffer layer, wherein the colored layer comprises dye."
  ],
  "description_excerpt": "The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more of the smaller components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than previous packages. Currently, integrated fan-out packages are becoming increasingly popular for their compactness. How to ensure the reliability of the integrated fan-out packages has become a challenge in the field.\n\nAspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.\n\nFIG. 1A to FIG. 1O are schematic cross-sectional views illustrating a manufacturing process of a package in accordance with some embodiments of the disclosure.\n\nFIG. 2 is a schematic cross-sectional view illustrating a package-on-package structure in accordance with some embodiments of the disclosure.\n\nFIG. 3 is a schematic cross-sectional view illustrating a package in accordance with some alternative embodiments of the disclosure.",
  "cpc": [
    "H10W 72/90",
    "H01L 21/565",
    "H01L 2224/02331",
    "H01L 2224/02333",
    "H01L 2224/02372",
    "H01L 2224/02379",
    "H01L 2224/0401",
    "H01L 23/3107",
    "H01L 24/03",
    "H01L 24/06",
    "H01L 24/09",
    "H10P 72/74",
    "H10P 72/7424",
    "H10W 70/09",
    "H10W 70/099",
    "H10W 70/60",
    "H10W 70/65",
    "H10W 70/655",
    "H10W 72/019",
    "H10W 72/073",
    "H10W 72/29",
    "H10W 72/874",
    "H10W 74/00",
    "H10W 74/014",
    "H10W 74/016",
    "H10W 74/111",
    "H10W 74/117",
    "H10W 90/00",
    "H10W 90/754"
  ],
  "ipc": [
    "H01L 23/00",
    "H01L 23/31",
    "H10W 74/01"
  ],
  "assignees": [
    "Taiwan Semiconductor Manufacturing Co TSMC Ltd"
  ],
  "inventors": [
    "Tian Hu",
    "Hung-Jui Kuo",
    "Yu-Hsiang Hu"
  ],
  "filing_date": "2019-08-22",
  "publication_date": "2021-11-09",
  "grant_date": "2021-11-09",
  "priority_date": "2018-09-27",
  "application_number": "US-201916548826-A",
  "family_id": "69946114",
  "cited_by_count": 7,
  "citations": [
    "US8350381B2",
    "US9048233B2",
    "US9064879B2",
    "US9372206B2",
    "US20130105991A1",
    "US9000584B2",
    "US9111949B2",
    "US9263511B2",
    "US9048222B2",
    "US9368460B2",
    "US9281254B2",
    "US20150287700A1",
    "US20160013144A1",
    "US9496189B2",
    "US20160071820A1",
    "US20160126220A1",
    "US20160379965A1"
  ]
}

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