Methods of forming wiring structures

{
  "publication_number": "US9281277B2",
  "country": "US",
  "kind": "B2",
  "title": "Methods of forming wiring structures",
  "abstract": "A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. A plurality of wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen.",
  "claims": [
    "1. A method of forming a wiring structure, the method comprising: forming, on a substrate, a first insulation layer that includes a plurality of trenches therein; forming a barrier layer in the plurality of trenches and on an upper surface of the first insulation layer; forming a metal layer on the barrier layer to fill the plurality of trenches; planarizing upper portions of the metal layer and the barrier layer until the upper surface of the first insulation layer is exposed to form a metal layer pattern having a first oxide layer thereon and a barrier layer pattern having a second oxide layer thereon; performing an ultraviolet (UV) pre-treatment process using UV and a reducing gas on the metal layer pattern and the barrier layer pattern to remove the first and second oxide layers thereon, respectively, so as to form a plurality of wiring patterns, wherein the plurality of wiring patterns include the barrier layer pattern and the metal layer pattern; forming a protection layer pattern directly on top surfaces of the plurality of wiring patterns, the protection layer pattern including a material having a high reactivity with respect to oxygen; partially removing the first insulation layer to form recesses between the plurality of wiring patterns; and forming a second insulation layer on the protection layer pattern and the first insulation layer to form an air gap between the plurality of wiring patterns.",
    "2. The method of claim 1, wherein the UV pre-treatment process and forming the protection layer pattern are performed in a vacuum chamber.",
    "3. The method of claim 1, wherein the reducing gas includes hydrogen gas and/or ammonia gas.",
    "4. The method of claim 1, wherein the UV pre-treatment process is performed at a temperature of about 250° C. to about 400° C.",
    "5. The method of claim 1, wherein the barrier layer includes Ta, TaN, TaC, TaCN, Ti, TiN and/or WN.",
    "6. The method of claim 1, wherein the metal layer includes copper.",
    "7. The method of claim 1, after performing the UV pre-treatment process, the method further comprising performing a plasma treatment process using ammonia gas.",
    "8. The method of claim 7, wherein the UV pre-treatment process and the plasma treatment process are performed in vacuum chambers that are different from each other.",
    "9. The method of claim 1, wherein the protection layer pattern includes aluminum nitride and/or cobalt.",
    "10. The method of claim 1, wherein forming the protection layer pattern comprises: forming the protection layer pattern using a metal nitride on the top surface of each of the plurality of wiring patterns; and forming a sacrificial layer pattern including a metal oxynitride on the first insulation layer.",
    "11. The method of claim 10, wherein forming the protection layer pattern comprises performing a chemical vapor deposition (CVD) process using an aluminum nitride precursor to form the sacrificial layer pattern including aluminum oxynitride and the protection layer pattern including aluminum nitride.",
    "12. The method of claim 10, wherein the sacrificial layer pattern is etched prior to partially removing the first insulation layer."
  ],
  "description_excerpt": "Example embodiments relate to wiring structures and methods of forming the same. More particularly, example embodiments relate to wiring structures including an air gap and methods of forming the same.\n\nAs semiconductor devices have been highly integrated, a distance between wiring structures has been reduced, and thus, a parasitic capacitance therebetween has been increased. Therefore, it is desired to develop a wiring structure having a low resistance and a low parasitic capacitance.\n\nExample embodiments provide wiring structures.\n\nExample embodiments provide methods of forming a wiring structure.\n\nAccording to some example embodiments, there is provided a wiring structure. The wiring structure includes a first insulation layer, multiple wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. Multiple wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen.\n\nIn some embodiments, the protection layer pattern may include a metal and/or a metal nitride.",
  "cpc": [
    "H10W 20/425",
    "H01L 21/7684",
    "H01L 21/76843",
    "H01L 21/76879",
    "H01L 21/76883",
    "H01L 23/5222",
    "H01L 23/528",
    "H01L 23/53223",
    "H01L 23/53238",
    "H01L 23/53266",
    "H01L 23/5329",
    "H01L 23/53295",
    "H01L 2924/00",
    "H01L 2924/0002",
    "H10D 64/011",
    "H10W 20/033",
    "H10W 20/037",
    "H10W 20/056",
    "H10W 20/057",
    "H10W 20/062",
    "H10W 20/072",
    "H10W 20/0765",
    "H10W 20/077",
    "H10W 20/42",
    "H10W 20/43",
    "H10W 20/46",
    "H10W 20/47",
    "H10W 20/48",
    "H10W 20/495"
  ],
  "ipc": [
    "H01L 21/768",
    "H10W 20/43"
  ],
  "assignees": [
    "Samsung Electronics Co Ltd"
  ],
  "inventors": [
    "Jong-min Baek",
    "Sang-Ho Rha",
    "Woo-Kyung You",
    "Sang-hoon Ahn",
    "Nae-in Lee",
    "Ki-chul Kim",
    "Jeon-Il LEE"
  ],
  "filing_date": "2014-10-30",
  "publication_date": "2016-03-08",
  "grant_date": "2016-03-08",
  "priority_date": "2013-12-23",
  "application_number": "US-201414527842-A",
  "family_id": "53400884",
  "cited_by_count": 494,
  "citations": [
    "US20070218677A1",
    "US8258627B2",
    "US20080124917A1",
    "US7741228B2",
    "US8084352B2",
    "US7879683B2",
    "US20090093100A1",
    "JP2009135172A",
    "US8310053B2",
    "US7842600B2",
    "US20100133648A1",
    "US8344474B2",
    "KR20130115935A"
  ]
}